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XRT72L58
EIGHT CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER
PRELIMINARY
REV. P1.1.2
XIX
R
X
E3 C
ONFIGURATION
& S
TATUS
R
EGISTER
2 (A
DDRESS
= 0
X
11) ........................................................ 453
R
X
E3 I
NTERRUPT
E
NABLE
R
EGISTER
- 2 (A
DDRESS
= 0
X
13) ................................................................. 453
R
X
E3 I
NTERRUPT
S
TATUS
R
EGISTER
- 2 (A
DDRESS
= 0
X
15) ................................................................. 454
R
X
E3 I
NTERRUPT
E
NABLE
R
EGISTER
- 2 (A
DDRESS
= 0
X
13) ................................................................. 454
R
X
E3 I
NTERRUPT
S
TATUS
R
EGISTER
- 2 (A
DDRESS
= 0
X
15) ................................................................. 454
R
X
E3 I
NTERRUPT
E
NABLE
R
EGISTER
- 2 (A
DDRESS
= 0
X
13) ................................................................. 455
R
X
E3 I
NTERRUPT
S
TATUS
R
EGISTER
- 2 (A
DDRESS
= 0
X
15) ................................................................. 455
R
X
E3 C
ONFIGURATION
& S
TATUS
R
EGISTER
1 (A
DDRESS
= 0
X
10) ........................................................ 456
R
X
E3 I
NTERRUPT
E
NABLE
R
EGISTER
- 2 (A
DDRESS
= 0
X
13) ................................................................. 456
R
X
E3 I
NTERRUPT
S
TATUS
R
EGISTER
- 2 (A
DDRESS
= 0
X
15) ................................................................. 456
R
X
E3 LAPD C
ONTROL
R
EGISTER
(A
DDRESS
= 0
X
18) ........................................................................... 457
R
X
E3 LAPD C
ONTROL
R
EGISTER
(A
DDRESS
= 0
X
18) ........................................................................... 457
7.0 diagnostic operation of the xrt72L58 framer ic .............................................................................. 458
Figure 213. Illustration of the Framer Local Loop-back path, within the XRT72L58 DS3/E3 Framer IC 458
8.0 High Speed HDLC Controller Mode of Operation ........................................................................... 460
8.1 C
ONFIGURING
THE
C
HANNEL
TO
OPERATE
IN
THE
H
IGH
S
PEED
HDLC C
ONTROLLER
M
ODE
................................. 460
T
ABLE
93: A
DDRESS
L
OCATIONS
OF
EACH
OF
THE
HDLC CONTROL R
EGISTERS
WITHIN
THE
XRT72L58 D
E
-
VICE
. .................................................................................................................................................... 460
HDLC C
ONTROL
R
EGISTER
(A
DDRESS
= 0
X
82) ..................................................................................... 460
8.2 O
PERATING
THE
H
IGH
S
PEED
HDLC C
ONTROLLER
............................................................................................ 460
8.2.1 Operating the Transmit HDLC Controller Block .................................................................................... 461
T
ABLE
94: D
ESCRIPTION
OF
E
ACH
OF
THE
T
RANSMIT
HDLC C
ONTROLLER
P
INS
.................................... 462
Figure 214. A Simple Illustration of an Outbound HDLC Frame, as assembled by the Transmit HDLC Con-
troller, when CRC-32 is selected. ........................................................................................................ 463
Figure 215. A Simple Illustration of an Outbound HDLC Frame, as assembled by the Transmit HDLC Con-
troller, when CRC-16 is selected. ........................................................................................................ 464
8.2.2 Operating the Receive HDLC Controller Block ..................................................................................... 464
T
ABLE
95: D
ESCRIPTION
OF
E
ACH
OF
THE
R
ECEIVE
HDLC C
ONTROLLER
P
INS
...................................... 465
ORDERING INFORMATION ........................................................................................ 466
PACKAGE DIMENSIONS ............................................................................................ 466
R
EVISION
H
ISTORY
................................................................................................................................ 467