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XRT72L56
SIX CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER
PRELIMINARY
REV. P1.1.2
8
B9
RxClk[0]
O
Receive Clock Output Signal for Serial and Nibble/Parallel Data Inter-
face:
Serial Mode Operation:
In the "serial" mode, this signal is a 44.736MHz clock output signal (for DS3
applications) or 34.368MHz clock output signal (for E3 applications). The
Receive Payload Data Output Interface will update the data via the RxSer
output pin, upon the rising edge of this clock signal.
The user is advised to design (or configure) the Terminal Equipment to sam-
ple the data on the "RxSer" pin, upon the falling edge of this clock signal.
Nibble-Parallel Mode Operation:
In Nibble-Parallel Mode, the XRT72L56 will derive this clock signal, from
the RxLineClk signal. The XRT72L56 will pulse this clock signal 1176 times
for each "inbound" DS3 frame (or 1074 times for each inbound “E3/ITU-T
G.832” frame, or 384 times for each inbound “E3/ITU-T G.751 frame). The
Receive Payload Data Output Interface will update the data, on the
"RxNib[3:0]" output pins upon the falling edge of this clock signal.
The user is advised to design (or configure) the Terminal Equipment to sam-
ple the data on the "RxNib[3:0] output pins, upon the rising edge of this
clock signal
B10
RxOHClk[0]/
RxHDLCClk[0]
O
O
Receive Overhead Output Clock Signal:
The XRT72L56 will output the Overhead bits (within the incoming DS3 or
E3 frames), via the "RxOH" output pin, upon the falling edge of this clock
signal.
The data on both the "RxOH" and "RxOHFrame" output pins should be
sampled on the rising edge of this clock..
N
OTE
:
This clock signal is always active.
Receive HDLC Output Clock:
When the HDLC controller is on, RxHDLCDat is updated by the 72L56 on
this clock signal.
B11
RxOH[0]/
RxHDLCDat6[0]
O
Receive Overhead Output Port:
All overhead bits received via the "Receive Section" of the Framer will be
output via this output pin, on the rising edge of RxOHClk.
Receive HDLC Data Output - 6:
This pin contains bit 6 RxHDLC data when the HDLC controller is turned on.
B12
TxFrame[0]
O
Transmit End of DS3 or E3 Frame Indicator:
A “high” (one bit period) indicates that the transmit payload data input inter-
face processes the last bit of a given DS3 or E3 frame data.
The purpose of this output pin is to alert the terminal equipment to begin
transmission of a new DS3 or E3 frame to the XRT72L56..
B13
TxOHFrame[0]/
TxHDLCClk[0]
O
Transmit Overhead Framing Pulse:
This output pin pulses "high" when the Transmit Overhead Data Input Inter-
face block is expecting the first Overhead bit, within a DS3 or E3 frame to be
applied to the TxOH input pin.
This pin is "high" for one clock period of TxOHClk.
Transmit HDLC Output Clock:
When the HDLC controller is on, TxHDLCDat is udpdated by the 72L56 on
this clock signal.
B14
TxAISEn[0]
I
See Description for Pin A22
PIN DESCRIPTION
FOR
THE
XRT72L56
P
IN
#
P
IN
N
AME
T
YPE
D
ESCRIPTION