á
FOUR CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER
XRT72L54
PRELIMINARY
REV. P1.1.2
132
General Flow of Framer Chip Interrupt Servicing
When any of the conditions, presented in
Table 6 oc-
curs, (if their Interrupts is enabled), then the Framer
will generate an interrupt request to the local P/C
by asserting the active-low interrupt request output
pin, INT. Shortly after the local P/C has detected
the activated INT signal, it will enter into the appropri-
ate user-supplied interrupt service routine. The first
task for the local P/C, while running this interrupt
service routine, may be to isolate the source of the in-
terrupt request down to the device level (e.g., the
XRT72L54 Framer Device), if multiple peripheral de-
vices exist in the user's system. However, once the
interrupting peripheral device has been identified, the
next task for the local P/C is to determine exactly
what feature or functional section within the device re-
quested the interrupt.
Determine the Channel Requesting the Interrupt
If the “interrupting” device turns out to be the
XRT72L54 3-Channel DS3/E3 Framer IC;
Determine the Functional Block(s) Requesting the
Interrupt
If the interrupt device turns out to be the XRT72L54
DS3/E3 Framer IC, then the local C/P must deter-
mine which functional block requested the interrupt.
Hence, upon reaching this state, one of the very first
things that the local C/P must do within the user
supplied Framer Interrupt Service routine, is to per-
form a read of the Block Interrupt Status Register
(Address = 0x05) within the XRT72L54 Framer de-
vice. The bit format of the Block Interrupt Status reg-
ister is presented below.
The Block Interrupt Status Register presents the in-
terrupt request status of each functional block, within
the chip. The purpose of the Block Interrupt Status
Register is to help the local P/C identify which func-
tional block(s) has requested the interrupt. Whichev-
er bit(s) are asserted in this register, identifies which
block(s) have experienced an interrupt-generating
condition as presented in
Table 6. Once the local P/
C has read this register, it can determine which
branch within the interrupt service routine that it must
follow, in order to properly service this interrupt.
The Framer further supports the Functional Block hi-
erarchy by providing the Block Interrupt Enable Reg-
ister (Address = 0x04). The bit format of this register
is identical to that for the Block Interrupt Status regis-
TABLE 9: A LISTING OF THE XRT72L54 FRAMER DEVICE INTERRUPT BLOCK REGISTER (FOR E3, ITU-T G.751
APPLICATIONS)
ADDRESS LOCATION
REGISTER NAME
0 x 04
Block Interrupt Enable Register
0 x 05
Block Interrupt Status Register
0 x 12
RxE3 Interrupt Enable Register -1
0 x 13
RxE3 Interrupt Enable Register -2
0 x 14
RxE3 Interrupt Status Register - 1
0 x 15
RxE3 Interrupt Status Register - 2
0 x 18
RxE3 LAPD Control Register
0 x 34
TxE3 LAPD Status/Interrupt Status
BLOCK INTERRUPT STATUS REGISTER (ADDRESS = 0X05)
BIT 7BIT 6BIT 5BIT 4BIT 3BIT 2BIT 1BIT 0
RxDS3/E3
Interrupt
Status
Not Used
TxDS3/E3
Interrupt
Status
One-Second
Interrupt
Status
RO
0
0000
000