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參數(shù)資料
| 型號： | XRT5897IV-F |
| 廠商： | Exar Corporation |
| 文件頁數(shù)： | 6/21頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC LIU E1 7CH 3.3V 100TQFP |
| 產(chǎn)品變化通告： | Product Discontinuation 18/Jan/2012 |
| 標(biāo)準(zhǔn)包裝： | 90 |
| 類型： | 線路接口裝置（LIU） |
| 驅(qū)動器/接收器數(shù)： | 7/7 |
| 規(guī)程： | E1 |
| 電源電壓： | 3.135 V ~ 3.465 V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 100-LQFP |
| 供應(yīng)商設(shè)備封裝： | 100-TQFP（14x14） |
| 包裝： | 托盤 |
XRT5897
14
Rev. 1.11
Transmitters
This device contains four identical ITU G.703 compliant
transmitters. The output stage of each transmitter is a
differential voltage driver. External resistors need to be
connected to the primary of output transformer. This is
necessary to maintain an accurate source impedance
that ensures compliance to ETSI 300 166 return loss
requirement.
TTL compatible dual rail transmit data signals are
supplied to TXPOS and TXNEG inputs. The transmitter
differential outputs TTIP and TRING are connected to the
output transformer primary through series 9.1W resistors.
All the four transmitters can be operated in two distinct
modes of operation referred to as “clocked” or “clockless”
modes. The operational mode is selected automatically
based on the signal provided to TXCLK input. If a clock is
present at this pin, the transmitter detects its presence
and operates in the clocked mode. In this mode, the
transmit input should be supplied with full-width NRZ
pulses. If a clock is not present at the TXCLK input (pin is
left open), the part operates in the clockless mode. In this
mode, RZ data should be supplied to the device. Each
transmit channel of XRT5897 has a duty cycle correction
circuitry. This enables the device to produce output
bipolar pulses fully compliant with G.703 despite having
TXCLK signal with 30% to 70% duty cycle.
Figure 4. CCITT G.703 Pulse Template
20%
488 ns
(244 + 244)
219 ns
(244 -- 25)
0%
50%
V = 100%
269 ns
(244 + 25)
194 ns
(244 -- 50)
Nominal pulse
244 ns
10%
20%
Note: V corresponds to the nominal peak value
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