參數資料
型號: XRT5794ES
廠商: Exar Corporation
英文描述: Evaluation System
中文描述: 評價體系
文件頁數: 3/11頁
文件大?。?/td> 715K
代理商: XRT5794ES
XRT5794ES
7
Rev. 2.00
Equipment-Side Signal Characteristics
All equipment-side connections at P1 and P2 are TTL
logic-levelcompatiblefor the inputs and outputs. Specific
signal types present at these pins are as follows.
LOS1 Through LOS4
These pins are the loss signal outputs (LOS) for the for
receive channels. A LOS output will go to a logic 1 state
when the input applied to the corresponding receiver is
less that the LOS threshold voltage.
RXPOS1 Through RXPOS4
The signal present at these pins is the positive half of the
dual-rail receive data. A positive bipolar input pulse at a
receiver input will produce a positive-going pulse at the
corresponding RXPOS output. Data pulse width at an
RXPOS output is approximately equal to the width of the
pulse applied to the reciever input at its 50% amplitude
point.
RXNEG1 Through RXNEG4
Thesignalpresentat thesepinsis thenegativehalfofthe
dual-rail receive data. A negative bipolar input pulse at a
receiver input will produce a positive-going pulse at the
corresponding RXNEG output. Data pulse width is the
same as described above for the RXPOS output.
TXCLK1 Through TXCLK4
These pins are the transmit clock inputs of four transmit
channels. For a specific channel, TXCLK is a 2.048 MHz
50%dutycyclesquarewavethatissynchronizedwiththe
data to be transmitted over that channel.
TXPOS1 Through TXPOS4
These pins are the positive rail inputs for the dual-rail
transmit
data
for
the
four
positive-going pulse at a TXPOS input will produce a
positive bipolar outout pulse at the corresponding
tranmit
channels.
A
tranmitter output. The signal applied to a TXPOS input
must be wider that the positive half cycle of the
corresponding TXCLK, and must also meet the set-up
andholdtimespecifiedintheXR-T5794datasheet.When
these conditions are met, the pulse width at the
transmitter output TXOUT is determined by the positive
going half-cycle of TXCLK .
TXNEG1 Through TXNEG4
These pins are the negative rail input for the dual-rail
transmit
data
for
the
four
positive-going pulse at a TXNEG input will produce a
negative bipolar output pulse at the corresponding
transmitter output. The pulse width conditions described
above for the TXPOS input also apply to TXNEG.
transmit
channels.
A
Operation Without TXCLK
Operation without TXCLK is possible if this pin is
connected to either DGND or DVDD. Transmit output
pulsewidthinthismodeofoperationisdeterminedbythe
widths of the pulsed applied to the TXPOS and TXNEG
inputs. Therefore, the data applied to these inputs must
be one-half width return-to-zero (RZ) pulses in order to
produce a normal width bipolar transmit output pulse.
DIP Switch Settings
On the demo board, the logic levels presented at all
control-type XR-T5794 input pins may be set with DIP
switches. The following circuit is used to switch logic
levels. EachIC input that is to be programmedhas a 10 K
W pull-up resistor connected to VDD. A SPAT DIP switch
section is also connected between this input and ground.
Therefore,whentheswitchleverisinthe“ON”positionas
marked on the switch body, the IC input is at a “Logic 0”
level.Forconvenience,asmall“1”and“0”thatindicateIC
pin logic level to switch position correspondence is
printed on the borad at the top end of each DIP switch.
相關PDF資料
PDF描述
XRT5894ES ()
XRT5894 Four-Channel E1 Line Interface (3.3V or 5.0V)(四通道E1 3.3V線接口單元)
XRT5897ES ()
XRT5897 Seven-Channel E1 Line Interface (3.3V or 5.0V)(七通道E1 3.3V線接口單元)
XRT5997 Seven-Channel E1 Line Interface Unit(7通道 E1線接口單元)
相關代理商/技術參數
參數描述
XRT5794ES-PLCC 功能描述:外圍驅動器與原件 - PCI 4 CH E1 AFE RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray
XRT5794ES-TQFP 功能描述:外圍驅動器與原件 - PCI 4 CH E1 AFE RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray
XR-T5794IJ 制造商:EXAR 制造商全稱:EXAR 功能描述:Quad E-1 Line Interface Unit
XRT5794IJ-F 功能描述:外圍驅動器與原件 - PCI RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray
XR-T5794IV 制造商:未知廠家 制造商全稱:未知廠家 功能描述:CEPT/T1 Interface