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參數(shù)資料
| 型號： | XRT5683AIP-F |
| 廠商： | Exar Corporation |
| 文件頁數(shù)： | 5/12頁 |
| 文件大小： | 0K |
| 描述： | IC PCM LINE INTERFACE 18PDIP |
| 產(chǎn)品變化通告： | XRT obsolescence 05/Mar/2012 |
| 標準包裝： | 20 |
| 功能： | PCM 線路接口芯片 |
| 接口： | PCM |
| 電路數(shù)： | 1 |
| 電源電壓： | 4.75 V ~ 5.25 V |
| 電流 - 電源： | 40mA |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 通孔 |
| 封裝/外殼： | 18-DIP（0.300"，7.62mm） |
| 供應商設備封裝： | 18-PDIP |
| 包裝： | 管件 |
XR-T5683A
2
Rev. 2.0.2
PIN CONFIGURATION
18 Lead PDIP (0.300”)
1
2
3
4
5
6
7
8
9
18
17
16
15
14
13
12
11
10
TVCC
TPOS
TCLK
TXDATA-
PDC
RXDATA-
RXDATA+
TE
TGND
TXDATA+
TNEG
RPOS
BIAS
TANK BIAS
RGND
RCLK
RNEG
RVCC
18 Lead SOIC (JEDEC, 0.300”)
18
1
10
9
2
3
4
5
6
7
15
14
13
12
11
17
16
8
PDC
RXDATA-
RXDATA+
TE
BIAS
TANK BIAS
RGND
RCLK
RVCC
TVCC
TPOS
TCLK
TXDATA-
TGND
TXDATA+
TNEG
RPOS
RNEG
PIN DESCRIPTION
Pin #
Symbol
Type
Description
1
PDC
Peak Detector Capacitor.
This pin should be connected to a 0.1
F capacitor.
2
RXDATA-
I
Receive Analog Input Positive.
Line analog input.
3
RXDATA+
I
Receive Analog Input Negative.
Line analog input.
4
TE
O
Tank Excitation Output.
This output connects to one side of the tank circuitry.
5
BIAS
O
Bias.
This output is to be connected to the center tap of the receive transformer.
6
TANK BIAS
O
Tank Bias.
The tank circuitry is biased via this output.
7
RGND
Receiver Ground.
To minimize ground interference a separate pin is used to ground the
receive section.
8
RCLK
O
Recovered Receive Clock.
Recovered clock signal to the terminal equipment.
9
RVCC
Receive Supply Voltage.
5V supply voltage to the receive section.
10
RNEG
O
Receive Negative Data.
Negative pulse data output to the terminal equipment (active low).
11
RPOS
O
Receive Positive Data.
Positive pulse data output to the terminal equipment (active low).
12
TNEG
I
Transmit Negative Data.
TNEG is valid while TCLK is high.
13
TXDATA+
O
Transmit Positive Output.
Transmit bipolar signal is driven to the line via a transformer.
14
TGND
Transmit Ground.
15
TXDATA-
O
Transmit Negative Output.
Transmit bipolar signal is driven to the line via a transformer.
16
TCLK
I
Transmit Clock.
Timing element for TPOS and TNEG.
17
TPOS
I
Transmit Positive Data.
TPOS is valid while TCLK is high.
18
TVCC
Transmit Supply Voltage.
5V supply voltage to the transmit section.
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