參數(shù)資料
型號(hào): XRD9818ACG
廠商: Exar Corporation
文件頁(yè)數(shù): 21/28頁(yè)
文件大小: 0K
描述: IC 16B CCD/CIS SIG PROC 28TSSOP
產(chǎn)品變化通告: Leaded UART, V&I Obsolescence 11/Apr/2011
標(biāo)準(zhǔn)包裝: 50
位數(shù): 16
通道數(shù): 3
功率(瓦特): 325mW
電壓 - 電源,模擬: 3 V ~ 3.6 V
電壓 - 電源,數(shù)字: 3 V ~ 3.6 V
封裝/外殼: 28-TSSOP(0.173",4.40mm 寬)
供應(yīng)商設(shè)備封裝: 28-TSSOP
包裝: 管件
xr
xr
XRD9818
3-CHANNEL 16-BIT LINEAR CCD/CIS SENSOR SIGNAL PROCESSOR
REV. 1.0.1
28
NOTICE
EXAR Corporation reserves the right to make changes to the products contained in this publication in order
to improve design, performance or reliability. EXAR Corporation assumes no responsibility for the use of
any circuits described herein, conveys no license under any patent or other right, and makes no
representation that the circuits are free of patent infringement. Charts and schedules contained here in are
only for illustration purposes and may vary depending upon a user’s specific application. While the
information in this publication has been carefully checked; no responsibility, however, is assumed for
inaccuracies.
EXAR Corporation does not recommend the use of any of its products in life support applications where
the failure or malfunction of the product can reasonably be expected to cause failure of the life support
system or to significantly affect its safety or effectiveness. Products are not authorized for use in such
applications unless EXAR Corporation receives, in writing, assurances to its satisfaction that: (a) the risk of
injury or damage has been minimized; (b) the user assumes all such risks; (c) potential liability of EXAR
Corporation is adequately protected under the circumstances.
Copyright 2000 EXAR Corporation
Datasheet June 2004.
REVISION HISTORY
Revision #
Date
Description
A1.0.0
08/20/02
1st release of the XRD9818 advanced data sheet.
A1.0.1
09/26/02
Modified Serial Port Read/Write timing diagrams, system specs INL, IRNMIN and IRNMAX
A1.1.0
10/17/02
Changed definition of PGA to 9bit & overall system gain 1x to 5x, redefined serial port
timing, added 3-CH & 1-CH timing diagrams for 8bit and 4bit data output modes,
A1.2.0
11/13/02
Added pin def, updated black diagram including VCMREF pin & removing LCLP pin,
updated 8bit 1-CH timing diagram
A1.3.0
1/30/03
Updated pin def type for CMREF. Updated serial port timing diagram. Added input signal
swing, reset pulse, Load pulse width and PGA spec’s to elec tables. Added register map &
bit definitions. Remove IB spec from CDS-S/H Specifications.
P1.0.0
11/14/03
Changed data sheet to Preliminary status. Added timing diagrams, functional descriptions
and electrical table updates to reflect part performance.
1.0.0
1/29/04
Released version. Updated electrical tables & document with char data, some minor text
edits to advance description, added performace data and application hook-up diagram.
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