Rev. 3.00 Figure 5. Equivalent Input Circuit Figure 6. Typical Circuit Connections APPLICATION NOTES Signals should not exceed V
參數(shù)資料
型號: XRD8785AID-F
廠商: Exar Corporation
文件頁數(shù): 12/15頁
文件大小: 0K
描述: IC ADC 8BIT PAR 15MSPS 24SOIC
標準包裝: 31
位數(shù): 8
采樣率(每秒): 20M
數(shù)據(jù)接口: 并聯(lián)
轉(zhuǎn)換器數(shù)目: 1
功率耗散(最大): 675mW
電壓電源: 模擬和數(shù)字
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 24-SOIC(0.295",7.50mm 寬)
供應(yīng)商設(shè)備封裝: 24-SOIC
包裝: 管件
輸入數(shù)目和類型: *
其它名稱: 1016-1330-5
XRD8785
6
Rev. 3.00
Figure 5. Equivalent Input Circuit
Figure 6. Typical Circuit Connections
APPLICATION NOTES
Signals should not exceed V
DD +0.5V or go below GND
–0.5V. All pins have internal protection diodes that will
protect them from short transients (<100
s) outside
the supply range.
AGND and DGND pins are connected internally
through the P-substrate. DC voltage differences be-
tween GND pins will cause undesirable internal sub-
strate currents.
The power supply (V
DD) and reference voltage (VRT &
V
RB) pins should be decoupled with 0.1F and 10F
capacitors to AGND, placed as close to the chip as
possible.
The digital outputs should not drive long wires or buses.
The capacitive coupling and reflections will contribute
noise to the conversion.
To avoid timing errors, use the rising edge of the sample
clock (CLK) to latch data from the XRD8785 to other
parts of the system.
The reference can be biased internally by shorting V
RT
to V
RTS and VRB to VRBS. This will generate 0.6V at VRB
and 2.6V at V
RT (see Figure 5).
If the internal reference pins V
RTS and/or VRBS are not
used, they should be left unconnected.
The output enable pin (OE) should not be left uncon-
nected. If not controlled by an active signal then it must
be tied to a logic low value.
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