參數(shù)資料
型號(hào): XRD64L42AIV
廠商: EXAR CORP
元件分類: ADC
英文描述: Dual 10-Bit 40MSPS CMOS ADC
中文描述: 2-CH 10-BIT SUCCESSIVE APPROXIMATION ADC, PARALLEL ACCESS, PQFP64
封裝: TQFP-64
文件頁(yè)數(shù): 7/16頁(yè)
文件大?。?/td> 212K
代理商: XRD64L42AIV
XRD64L42
7
Rev. P2.10
ELECTRICAL CHARACTERISTICS TABLE (CONT'D)
Test Conditions (Unless Otherwise Specified)
T
A
= 25
°
C AV
DD
= DV
DD
= +3.0V, VIN = GND to +2.5V, V
RLF
= GND, V
RHF
= +2.5V and Fs = 40MSPS, 50% Duty
Cycle, Differential Input Mode
Symbol
Parameter
Min.
Typ.
Max.
Unit
Conditions
DYNAMIC PERFORMANCE Fs = 40MHz
SNR
Signal-to-Noise Ratio
Not Including Harmonics
fin = 1.0 MHz
58
60
dB
fin = 4.0 MHz
57
60
dB
fin = 10.0 MHz
57
59
dB
SINAD
Signal-to Noise and
Distortion
Including Harmonics
fin = 1.0 MHz
58
60
dB
fin = 4.0 MHz
57
59
dB
fin = 10 MHz
56
58
dB
ENOB EFFECTIVE NUMBER OF BITS
fin = 1.0 MHz
9.3
9.7
Bit
fin = 4.0 MHz
9.2
9.5
Bit
fin = 10 MHz
9.0
9.2
Bit
SFDR SPURIOUS FREE DYNAMIC RANGE
SFDR
fin = 1.0 MHz
70
dB
Crosstalk
fin = 1.0 MHz
fin1 = 2.5 MHz
fin2 = 3.5 MHz
75
dB
IMD
70
dB
Intermodulation Distortion
CONVERSION AND TIMING CHARACTERISTICS (CL = 10pF)
MAXCON
MINCON
Lat
APJT
tr
tf
tpd
Maximum Conversion
Minimum Conversion
Latency
Aperture Jitter Time
Digital Output Rise Time
Digital Output Fall Time
Output Data Propagation
Delay
Output Data Enable
Delay
Output Data Disable
Delay
Clock Duty Cycle
40
50
100
17
12
3
3
6
MSPS
KSPS
cycles
ps
ns
ns
ns
Guaranteed by Design
Peak-to Peak
25
tden
6
20
ns
Guaranteed by Design
tdis
5
20
ns
Guaranteed by Design
CLKDC
40
50
60
%
Guaranteed by Design
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