參數(shù)資料
型號(hào): XRD6414AIQ
廠商: EXAR CORP
元件分類: ADC
英文描述: CMOS 10-Bit, 20 MSPS, High Speed Analog-to-Digital Converter with 4:1 Input Analog Multiplexer
中文描述: 4-CH 10-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQFP32
封裝: 7 X 7 MM, 1.40 MM HEIGHT, TQFP-32
文件頁(yè)數(shù): 7/16頁(yè)
文件大?。?/td> 204K
代理商: XRD6414AIQ
XRD6414
7
Rev. 1.00
THEORY OF OPERATION
V
IN
Analog Input
This part has a switched capacitor type input circuit. The
input impedance changes with the phase of the input
clock. V
IN
is sampled at the low to high clock transition
and the digital data changes at the low to high clock
transition. The diagram Figure 4. shows an equivalent
input circuit.
Figure 4. Equivalent Input Circuit
100
+
V
RT
+ V
RB
2
V
IN
AGND
100
18pF
1.5pF
AV
DD
CLK
C
L
CLK
5pF
OFW Overflow (Output)
This signal indicates when the Analog Input (V
IN
) goes
above V
RT
. The pin is normally at a low logic level. When
V
IN
> V
RT
, OFW will go high and the data bits (DB0 – DB9)
will show full scale (i.e. all 1s).
OE Output Enable (Input)
This signal controls the 3-state drivers on the digital
outputs DB0 – DB9 and OFW. During normal operation
OE should be held low so that all outputs are enabled.
When OE is driven high DB0 – DB9 and OFW go into high
impedance mode. This control operates asynchronous to
the clock and will only control the output drivers. The
internal output register will get updated if the clock is
running while the outputs are in three-state mode.
OE
DBO-DB9
OFW
0
Enabled
Enabled
1
Three-Stated
Three-Stated
Table 1. Output Enable
Power Supply Sequencing
There are no power supply sequencing issues if DV
DD
and AV
DD
of the XRD6414 are driven from the same
supply. Best parametric results, however, are obtained
when DV
DD
and AV
DD
are driven from separate supplies.
When DV
DD
and AV
DD
are driven separately, AV
DD
must
come up at the same time or before DV
DD
, and go down at
the same time or after DV
DD
. If the power supply
sequencing in this case is not followed, then damage may
occur to the product due to current flow through the
source-body junction diodes between DV
DD
and AV
DD
. A
low threshold schottky diode placed locally between
DV
DD
and AV
DD
can prevent damage to the XRD6414.
Logic Output Interface
The digital output drive circuitry of the XRD6414 was
designed to operate separately from the analog supplies.
The DV
DD
pin of the XRD6414 is a separate power supply
dedicated to the logic output drivers. DV
DD
is not
connected internally with any of the other power supplies.
Figure 5.illustrates the power supply circuity of the
XRD6414.
DV
DD
and DGND connect directly to the digital logic
power of the user’s system isolating the analog and digital
power supplies and grounds. DGND is not common to the
XRD6414 substrate. The XRD6414 substrate is common
only to the packages’ AGND pins. Best spectral
performance is obtained when DV
DD
is lowered to 3.3V.
See the power supply sequencing section if AV
DD
and
DV
DD
are powered separately.
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