參數(shù)資料
型號(hào): XRD6414
廠商: Exar Corporation
英文描述: CMOS 10-Bit, 20 MSPS, High Speed Analog-to-Digital Converter with 4:1 Input Analog Multiplexer
中文描述: 的CMOS 10位,20 MSPS的,高速模擬數(shù)字轉(zhuǎn)換器的4:1輸入模擬多路復(fù)用器
文件頁(yè)數(shù): 5/16頁(yè)
文件大?。?/td> 204K
代理商: XRD6414
XRD6414
5
Rev. 1.00
ELECTRICAL CHARACTERISTICS
(CONT’D)
Symbol
Digital Inputs
V
IH
V
IL
I
IN
Parameter
Min.
Typ.
Max.
Unit
Conditions
Digital Input High Voltage
Digital Input Low Voltage
DC Leakage Currents
6
CLK, OE, PD, A0, A1
Input Capacitance
3.5
V
V
1.5
5
5
A
Between AGND and AV
DD
pF
Digital Outputs
V
OH
V
OL
I
OZ
t
DL
t
DEN
t
DHZ
Output High Voltage
4.5
V
Output Low Voltage
0.4
V
High-Z Leakage
Data Valid Delay
2
–10
10
A
OE = high, or PD = high
10
12
14
ns
Data Enable Delay
10
12
14
ns
Data High-Z Delay
7
8
9
ns
Pipeline Delay (Latency)
3
cycles
Time delay between CLK and data
output
Power Supplies
I
DD
(PD)
Power Down (I
DD
)
0.3
0.5
mA
PD = high, excluding current
through reference ladder
AV
DD
DV
DD
I
DD
Operating Voltage
7,8
Logic Power Supply
9
4.5
5.0
5.5
V
2.7
5.5
V
Supply Current (I
DD
)
24
32
mA
PD = low
Notes
1
Tester measures code transitions by dithering the voltage of the analog nput (V
IN
). The difference between the measured and the
ideal code width (V
REF
/1024) is the DNL error. The INL error is the maximum distance (in LSBs) from the best fit line to
any transition voltage. Accuracy is a function of the sampling rate (FS).
2
Specified values guarantee functionality. Refer to other parameters for accuracy.
3
Guaranteed. Not tested.
4
–1 dB bandwidth is a measure of performance of the A/D input stage (S/H + amplifier). Refer to other parameters for accuracy
within the specified bandwidth.
5
See V
IN
equivalent circuit. Switched capacitor analog input requires driver with low output resistance.
6
All nputs have diodes to AV
DD
and AGND. Input DC currents will not exceed specified imits for any nput voltage between AGND
and AV
DD
.
7
The GND pins are connected through the silicon substrate. Connect all GND pins together at the package and to the analog
ground plane. DGND and GND are connected through junction diodes. See logic output interface section.
8
The V
DD
pins should be tied together at the package.
9
See logic output interface section.
Specifications are subject to change without notice
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