參數(shù)資料
型號: XRD6406
廠商: Exar Corporation
英文描述: CMOS 6 MSPS, 10-Bit, High Speed Analog-to-Digital Converter
中文描述: 的CMOS 6 MSPS的10位,高速模擬數(shù)字轉(zhuǎn)換器
文件頁數(shù): 3/12頁
文件大?。?/td> 238K
代理商: XRD6406
XRD6406
3
Rev. 1.00
ELECTRICAL CHARACTERISTICS TABLE
Unless Otherwise Specified: AV
DD
= DV
DD
= 5V, FS = 6MHz (50% Duty Cycle),
V
RT
= 4.0, V
RB
= 1.0, T
A
= 25
°
C
25
°
C
Typ
Parameter
Symbol
Min
Max
Units
Test Conditions/Comments
KEY FEATURES
Resolution
Maximum Sampling Rate
10
Bits
MHz
FS
6
ACCURACY (A Grade)
1
Differential Non-Linearity
Integral Non-Linearity
DNL
INL
+1
+2
LSB
LSB
Best Fit Line
(Max INL -- Min INL)/2
Zero Scale Error
Gain Error
EZS
EFS
10
LSB
LSB
6
REFERENCE VOLTAGES
Positive Ref. Voltage
2,3
Negative Ref. Voltage
2,3
Differential Ref. Voltage
2,3
LadderResistance
LadderTemp. Coefficient
2
Top Internal Reference
Bottom Internal Reference
V
RT
V
RB
V
REF
AV
DD
V
V
V
ppm/
°
C
V
V
AGND
1.0
AV
DD
V
REF
= V
RT
-- V
RB
R
L
1400
2000
R
TCO
V
RTS
V
RBS
4
1
V
RT
connected to V
RTS
&
V
RB
connected to V
RBS
ANALOG INPUT
Input Bandwidth (--1 dB)
2,4
Input Voltage Range
Input Capacitance (Sample)
2,5
Input Capacitance (Convert)
2,5
Aperture Delay
2
Aperture Uncertainty
2
(J itter)
BW
V
IN
C
IN
25
MHz
V
pF
pF
ns
ps
V
RB
V
RT
40
12
30
25
7
t
AP
t
AJ
25
50
DIGITAL INPUTS
Logical “1” Voltage
Logical “0” Voltage
DC Leakage Currents
2,6
CLK
OE
Input Capacitance
2
Clock Timing
(
See Figure 1
)
Clock Period
2
Rise & Fall Time
2,7
“High” Pulse Width
2,3
“Low” Pulse Width
2,3
Duty Cycle
2,3
V
IH
V
IL
I
IN
4
V
V
1
V
IN
=DGND to DV
DD
5
5
5
μ
A
μ
A
pF
1/FS
t
R
, t
F
t
PWH
t
PWL
167
ns
ns
ns
ns
%
2
84
84
50
DIGITAL OUTPUTS
C
OUT
=15 pF
Logical “1” Voltage
Logical “0” Voltage
3-state Leakage
Data Valid Delay
Data Enable Delay
Data 3-state Delay
V
OH
V
OL
I
OZ
t
DL
t
DEN
t
DHZ
4.5
V
V
μ
A
ns
ns
ns
I
LOAD
= 4mA
I
SINK
= 4mA
V
OUT
=DGND to DV
DD
0.4
10
40
25
25
45
30
30
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