參數資料
| 型號： | XRA1207IL24-F |
| 廠商： | Exar Corporation |
| 文件頁數： | 12/17頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC I/O EXPANDER I2C 16B 24QFN |
| 標準包裝： | 490 |
| 接口： | I²C，SM 總線 |
| 輸入/輸出數： | 16 |
| 中斷輸出： | 是 |
| 頻率 - 時鐘： | 400kHz |
| 電源電壓： | 1.65 V ~ 3.6 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 24-VFQFN 裸露焊盤 |
| 供應商設備封裝： | 24-QFN（4x4） |
| 包裝： | 托盤 |
| 其它名稱： | 1016-1720 |
XRA1207
4
16-BIT I2C/SMBUS GPIO EXPANDER WITH INTEGRATED LEVEL SHIFTERS
REV. 1.0.0
1.0 FUNCTIONAL DESCRIPTIONS
1.1
I2C-bus Interface
The I2C-bus interface is compliant with the Standard-mode and Fast-mode I2C-bus specifications. The I2C-bus
interface consists of two lines: serial data (SDA) and serial clock (SCL). In the Standard-mode, the serial clock
and serial data can go up to 100 kbps and in the Fast-mode, the serial clock and serial data can go up to 400
kbps.
The first byte sent by an I2C-bus master contains a start bit (SDA transition from HIGH to LOW when SCL is
HIGH), 7-bit slave address and whether it is a read or write transaction. The next byte is the sub-address that
contains the address of the register to access. The XRA1207 responds to each write with an acknowledge
(SDA driven LOW by XRA1207 for one clock cycle when SCL is HIGH). The last byte sent by an I2C-bus
master contains a stop bit (SDA transition from LOW to HIGH when SCL is HIGH). See Figures 3 - 5 below.
For complete details, see the I2C-bus specifications.
FIGURE 3. I C START AND STOP CONDITIONS
SDA
SCL
S
P
START condition
FIGURE 4. MASTER WRITES TO SLAVE
SW
A
AP
SL AVE
AD D R ESS
CO M M A ND
BYT E
DA T A
BYT E
W h ite b lock: h o st to X R A 1 20 x
G rey block: X R A 12 0 x to h ost
FIGURE 5. MASTER READS FROM SLAVE
SW
A
AR
SLAVE
ADDRESS
COMMAND
BYTE
White block: host to XRA120x
Grey block: XRA120x to host
A
S
SLAVE
ADDRESS
nDATA
ANA
P
LAST DATA
2
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| XRA1207IL24TR-F | 功能描述:接口-I/O擴展器 16 Bit I2C GPIO Expander RoHS:否 制造商:NXP Semiconductors 邏輯系列: 輸入/輸出端數量: 最大工作頻率:100 kHz 工作電源電壓:1.65 V to 5.5 V 工作溫度范圍:- 40 C to + 85 C 安裝風格:SMD/SMT 封裝 / 箱體:HVQFN-16 封裝:Reel |
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