Figure 30 shows that the phase re" />
參數(shù)資料
型號: XR88C681J-F
廠商: Exar Corporation
文件頁數(shù): 56/101頁
文件大?。?/td> 0K
描述: IC UART CMOS DUAL 44PLCC
標準包裝: 27
特點: *
通道數(shù): 2,DUART
FIFO's: 1 字節(jié),3 字節(jié)
電源電壓: 4.75 V ~ 5.25 V
帶并行端口:
帶CMOS:
安裝類型: 表面貼裝
封裝/外殼: 44-LCC(J 形引線)
供應(yīng)商設(shè)備封裝: 44-PLCC(16.59x16.59)
包裝: 管件
其它名稱: 1016-1329
XR88C681
58
Rev. 2.11
Figure 30. Receiver (1X) Sampling, if the RX Clock is Slightly Faster Than the TX Clock
Figure 30 shows that the phase relationship between the Receiver’s sampling point and each serial data bit is changing.
In this case, the Receiver is sampling each serial data bit, earlier and earlier in the bit period, with each successive data
bit. This phenomenon is known as receiver drift. If there is no correction for receiver drift, there will be many errors in the
transmission and reception of this serial data, as depicted in
Figure 31.
Actual Data
Received Data
Figure 31. Illustration of an Error due to Receiver Drift
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Figure 31 shows the Receiver sampling an eight bit string of data with bit pattern 0101010. It is interesting to note that, in
Figure 31, the Receiver sampled 01010010. It should be noted that Receiver drift can also be a problem is the local
Receiver is slower than the remote Transmitter clock.
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