參數(shù)資料
型號: XR88C681CP/40
廠商: Exar Corporation
文件頁數(shù): 52/101頁
文件大小: 0K
描述: IC UART CMOS DUAL 40PDIP
產(chǎn)品變化通告: Leaded UART, V&I Obsolescence 11/Apr/2011
標準包裝: 9
特點: *
通道數(shù): 2,DUART
FIFO's: 1 字節(jié),3 字節(jié)
電源電壓: 4.75 V ~ 5.25 V
帶并行端口:
帶CMOS:
安裝類型: 通孔
封裝/外殼: 40-DIP(0.600",15.24mm)
供應商設備封裝: 40-PDIP
包裝: 管件
XR88C681
54
Rev. 2.11
D.3 Counter/Timer
The Timing Control Block also contains a 16 bit
Counter/Timer (C/T). The C/T is a programmable 16 bit
down-counter which can use one of several timing
sources as its input.
Figure 28 presents a block diagram
of the circuitry surrounding the C/T. The selection of these
timing sources for the Counter/Timer can be made by
writing the appropriate data to ACR[6:4] (Auxiliary Control
Register bits 6 through 4). Please see
Table 16 for the
relationship between the Counter/Timer mode, the
Timing Source and ACR[6:4]. The C/T output is available
to the Clock Select Registers for use as a programmable
bit rate generator for both Transmitters and Receivers.
Counter/Timer
Preset Registers
(CTUR, CTLR)
IP2
Divide by 16
Oscillator
Circuit
TXCA
TXCB
ACR[4-6]
C/T_RDY
(OP3)
to 32:1 MUXs
Divide by 16
Figure 28. A Block Diagram of the Circuitry Associated with the
Counter/Timer
Bit 6
Bit 5
Bit 4
C/T Mode
Timing Source
0
Counter
External Input - IP2
0
1
Counter
TXCA 1X - Clock of Channel A Transmitter
0
1
0
Counter
TXCB 1X - Clock of Channel B Transmitter
0
1
Counter
X1/CLK Input Divided by 16
1
0
Timer
External Input - IP2
1
0
1
Timer
External Input - IP2, Divided by 16
1
0
Timer
X1/CLK Input
1
Timer
X1/CLK Input Divided by 16
Table 16. ACR[6:4] Bit Field Definition - C/T
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