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參數(shù)資料
| 型號： | XR88C192IVTR-F |
| 廠商： | Exar Corporation |
| 文件頁數(shù)： | 31/32頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC UART FIFO DUAL 44LQFP |
| 標(biāo)準(zhǔn)包裝： | 1,000 |
| 特點： | * |
| 通道數(shù)： | 2，DUART |
| FIFO's： | 16 字節(jié) |
| 電源電壓： | 2.97 V ~ 5.5 V |
| 帶自動流量控制功能： | 是 |
| 帶CMOS： | 是 |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 44-LQFP |
| 供應(yīng)商設(shè)備封裝： | 44-LQFP（10x10） |
| 包裝： | 帶卷 (TR) |
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XR88C92/192
8
Rev. 1.33
the parallel outputs OP3 through OP7 to provide dis-
crete interrupt outputs for the transmitters, the receiv-
ers, and the C/T. See 'Configuring Multi-purpose Out-
puts' section for details.
DATA BUS BUFFER (D0 - D7)
The data bus buffer provides the interface between the
external and internal data buses. It is controlled by the
internal control logic to allow read and write data transfer
operations to occur between the controlling CPU and
XR88C92/192 by way of the eight parallel data lines (D0
through D7).
MULTI-PURPOSE INPUTS (IP0 - IP6)
The states of the seven multi-purpose inputs (IP0
through IP6) can be read from the internal register IPR
(address 0x0D). The bits in this register are the comple-
ments of the actual inputs - for example, if the IP0 is low,
the corresponding bit in the IPR, bit-0 is a logic '1'. Each
of these inputs also has an alternate control function
capability. The alternate functions can be enabled/
disabled on a bit-by-bit basis. The following table shows
how each of these inputs is configured for its special
function:
Interrupt Status Register (ISR, address 0x05) for de-
tails. The IPCR bits are cleared when the CPU reads the
register. Also see the Baud Rate Table on page 18.
MULTI-PURPOSE OUTPUTS (OP0 - OP7)
The eight output pins (OP0 - OP7) can either be used
as general purpose outputs or can be used for alternate
functions representing various conditions using
- Mode Registers 1 and 2 (MR1A, MR1B, MR2A, MR2B)
- Output Port Configuration Register (OPCR)
- Set Output Port Register (SOPR), and
- Reset Output Port Register (ROPR).
OP0 and OP1:
The output OP0 can function as the channel A request-
to-send (-RTSA) output for either the transmitter (MR2A
bit-5 = 1) or the receiver (MR1A bit-7 = 1). Note that only
one of these bits should be set to '1' at a given time. See
the description of the transmitter RTS and receiver RTS
in the 'Transmitter' and 'Receiver' sections of this
datasheet respectively. The output OP1 acts as the
channel B request-to-send (-RTSB) output and is con-
trolled in a similar way by the channel B registers.
Input
Function
Programming
IP0
-CTSA
Set MR2A bit-4 = 1
IP1
-CTSB
Set MR2B bit-4 = 1
IP2
C/T Ext. Clk
Set ACR[6:4] = 000
IP3
TxA Ext. Clk
Set CSRA[3:0] = 1110 or 1111
IP4
RxA Ext. Clk Set CSRA[7:4] = 1110 or 1111
IP5
TxB Ext. Clk
Set CSRB[3:0] = 1110 or 1111
IP6
RxB Ext. Clk Set CSRB[7:4] = 1110 or 1111
Four change-of-state detectors are associated with
inputs IP0, IP1, IP2, and IP3. If a high-to-low or low-to-
high transition occurs on any of these inputs, the
corresponding bit in the input port change register
(IPCR - address 0x04) will be set accordingly. The
sampling clock of the change detectors is the XTAL1/
96 tap of the baud rate generator, which is 38.4kHz if
XTAL1 is 3.6864MHz. A new input level must be sampled
on two consecutive sampling clocks to detect a change.
Also, users can program the XR88C92/192 to allow a
change of state in any of the inputs IP0 through IP3 to
generate an interrupt to the CPU. See description of the
XTAL1
XTAL2
Y1
C1
22-47pF
C2
22-47pF
3.6864MHz
200 - 500 k
XR88C92/192
Figure 1: Crystal Connection
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