REV. 1.1.1 HIGH PERFORMANCE DUART WITH 64-BYTE FIFO 4.3.2 IER versus Receive/Transmit FIFO Polled Mode Operation When FCR " />
參數(shù)資料
型號: XR68M752IL32-F
廠商: Exar Corporation
文件頁數(shù): 20/54頁
文件大小: 0K
描述: IC UART FIFO 64B DUAL 32QFN
標準包裝: 490
特點: *
通道數(shù): 2,DUART
FIFO's: 64 字節(jié)
規(guī)程: RS232,RS422,RS485
電源電壓: 1.62 V ~ 3.63 V
帶自動流量控制功能:
帶IrDA 編碼器/解碼器:
帶故障啟動位檢測功能:
帶調(diào)制解調(diào)器控制功能:
帶CMOS:
安裝類型: 表面貼裝
封裝/外殼: 32-VFQFN 裸露焊盤
供應商設備封裝: 32-QFN 裸露焊盤(5x5)
包裝: 托盤
XR16M752/XR68M752
27
REV. 1.1.1
HIGH PERFORMANCE DUART WITH 64-BYTE FIFO
4.3.2
IER versus Receive/Transmit FIFO Polled Mode Operation
When FCR BIT-0 equals a logic 1 for FIFO enable; resetting IER bits 0-3 enables the XR16M752 in the FIFO
polled mode of operation. Since the receiver and transmitter have separate bits in the LSR either or both can
be used in the polled mode by selecting respective transmit or receive control bit(s).
A. LSR BIT-0 indicates there is data in RHR or RX FIFO.
B. LSR BIT-1 indicates an overrun error has occurred and that data in the FIFO may not be valid.
C. LSR BIT 2-4 provides the type of receive data errors encountered for the data byte in RHR, if any.
D. LSR BIT-5 indicates THR is empty.
E. LSR BIT-6 indicates when both the transmit FIFO and TSR are empty.
F. LSR BIT-7 indicates a data error in at least one character in the RX FIFO.
IER[0]: RHR Interrupt Enable
The receive data ready interrupt will be issued when RHR has a data character in the non-FIFO mode or when
the receive FIFO has reached the programmed trigger level in the FIFO mode.
Logic 0 = Disable the receive data ready interrupt (default).
Logic 1 = Enable the receiver data ready interrupt.
IER[1]: THR Interrupt Enable
This bit enables the Transmit Ready interrupt which is issued whenever the THR becomes empty in the non-
FIFO mode or when spaces in the FIFO is above the programmed trigger level in the FIFO mode. If the THR is
empty when this bit is enabled, an interrupt will be generated.
Logic 0 = Disable Transmit Ready interrupt (default).
Logic 1 = Enable Transmit Ready interrupt.
IER[2]: Receive Line Status Interrupt Enable
If any of the LSR register bits 1, 2, 3, 4 or 7 is a logic 1, it will generate an interrupt to inform the host controller
about the error status of the current data byte in FIFO. LSR bit-1 generates an interrupt immediately when the
character has been received. LSR bit-7 is set if any character in the RX FIFO has a parity or framing error, or is
a break character. LSR[4:2] always show the error status for the received character available for reading from
the RX FIFO. If IER[2] = 1, an LSR interrupt will be generated as long as LSR[7] = 1, ie. the RX FIFO contains
at lease one character with an error.
Logic 0 = Disable the receiver line status interrupt (default).
Logic 1 = Enable the receiver line status interrupt.
IER[3]: Modem Status Interrupt Enable
Logic 0 = Disable the modem status register interrupt (default).
Logic 1 = Enable the modem status register interrupt.
IER[4]: Sleep Mode Enable (requires EFR bit-4 = 1)
Logic 0 = Disable Sleep Mode (default).
Logic 1 = Enable Sleep Mode. See Sleep Mode section for further details.
IER[5]: Xoff Interrupt Enable (requires EFR bit-4=1)
Logic 0 = Disable the software flow control, receive Xoff interrupt (default).
Logic 1 = Enable the receive Xoff interrupt. See Software Flow Control section for details.
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