C1 220pF 5%" />
參數(shù)資料
型號(hào): XR2211ACD-F
廠商: Exar Corporation
文件頁(yè)數(shù): 7/24頁(yè)
文件大?。?/td> 0K
描述: IC FSK DEMOD/TONE DECOD 14SOIC
標(biāo)準(zhǔn)包裝: 56
功能: FSK 解調(diào)器,音頻解碼器
電源電壓: 4.5 V ~ 20 V
電流 - 電源: 5mA
功率(瓦特): 900mW
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 14-SOIC(0.154",3.90mm 寬)
供應(yīng)商設(shè)備封裝: 14-SOIC
包裝: 管件
包括: 載波檢測(cè)
其它名稱: 1016-1308-5
XR-2211A
15
Rev. 1.04
Figure 12. Circuit Connection for Tone Detection
Loop
Phase
Detect
11
C1
220pF
5%
R1
200K
1%
8
FSK
Comp.
VCC
7
Internal
Reference
0.1
F
10
VCO
14
13
12
R0
20K
1%
C0
50nF
5%
Rx
5K
2
0.1
F
Input
Tone
Lock
Detect
Comp.
Tune
Fine
6 LDOQ
RL2
5.1K
RL3
5.1K
Logic Output
5 LDOQN
3
CD
80nF
RD
470K
Quad
Phase
Detect
VCC
VCO
+
FSK Decoding with Carrier Detect
The lock detect section of XR-2211A can be used as a
carrier
detect
option
for
FSK
decoding.
The
recommended circuit connection for this application is
shown in
Figure 11. The open collector lock detect output,
pin 6, is shorted to data output (pin 7). Thus, data output
will be disabled at “l(fā)ow” state, until there is a carrier within
the detection band of the PLL and the pin 6 output goes
“high” to enable the data output.
Note: Data Output is “Low” When No Carrier is Present.
The minimum value of the lock detect filter capacitance
CD is inversely proportional to the capture range, +Dfc.
This is the range of incoming frequencies over which the
loop can acquire lock and is always less than the tracking
range. It is further limited by C1. For most applications, Dfc
>
Df/2. For RD = 470KW, the approximate minimum value
of CD can be determined by:
C
D
§ 16
Df
C in
mF and f in Hz.
C in
mF and f in Hz.
With values of CD that are too small, chatter can be
observed on the lock detect output as an incoming signal
frequency
approaches
the
capture
bandwidth.
Excessively large values of CD will slow the response time
of the lock detect output. For Caller I.D. applications
choose CD = 0.1mF.
Tone Detection
Figure 12 shows the generalized circuit connection for
tone detection. The logic outputs, LDOQN and LDOQ at
pins 5 and 6 are normally at “high” and “l(fā)ow” logic states,
respectively. When a tone is present within the detection
band of the PLL, the logic state at these outputs become
reversed for the duration of the input tone. Each logic
output can sink 5mA of load current.
Both outputs at pins 5 and 6 are open collector type
stages, and require external pull-up resistors RL2 and
RL3, as shown in Figure 12.
With reference to
Figure 3 and Figure 12, the functions of
the external circuit components can be explained as
follows: R0 and C0 set VCO center frequency; R1 sets the
detection bandwidth; C1 sets the low pass-loop filter time
constant and the loop damping factor.
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