REV. 1.3.0 2-CH FULL-SPEED USB UART 3.3.14 GPIO_INT_MASK Register Description (Read/Write) Enables / disables generation of a USB " />
參數(shù)資料
型號(hào)： XR21V1412IL32TR-F
廠商： Exar Corporation
文件頁(yè)數(shù)： 18/32頁(yè)
文件大?。?/td> 0K
描述： IC USB UART FIFO FULL SPD 32QFN
產(chǎn)品培訓(xùn)模塊： XR21V141x Full-Speed USB UART Family
標(biāo)準(zhǔn)包裝： 3,000
特點(diǎn)： *
通道數(shù)： 2，DUART
FIFO's： 128 字節(jié)，384 字節(jié)
規(guī)程： USB 2.0
電源電壓： 2.97 V ~ 3.63 V
帶自動(dòng)流量控制功能： 是
安裝類型： 表面貼裝
封裝/外殼： 32-VFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝： 32-QFN 裸露焊盤（5x5）
包裝： 帶卷 (TR)
配用： 1016-1301-ND - EVAL BOARD FOR XR21V1412IL
XR21V1412
25
REV. 1.3.0
2-CH FULL-SPEED USB UART
3.3.14
GPIO_INT_MASK Register Description (Read/Write)
Enables / disables generation of a USB interrupt packet at the change of state of GPIO pins when they are
configured as inputs.
GPIO_INT_MASK[5:0]: GPIOx Interrupt Mask
Logic 0 = A change on this input causes the device to generate an interrupt packet.
Logic 1 = A change on this input does not cause the device to generate an interrupt packet.
GPIO_INT_MASK[7:6]: Reserved
These register bits are reserved and should be ’0’.
3.3.15
GPIO_SET Register Description (Read/Write)
Writing a ’1’ in this register drives the GPIO output high. Writing a ’0’ to a bit has no effect. Bits 7-6 are unused
and should be ’0’.
3.3.16
GPIO_CLEAR Register Description (Read/Write)
Writing a ’1’ in this register drives the GPIO output low. Writing a ’0’ to a bit has no effect. Bits 7-6 are unused
and should be ’0’.
3.3.17
GPIO_STATUS Register Description (Read-Only)
This register reports the current state of the GPIO pin.
3.4
UART Custom Registers
3.4.1
CUSTOM Register Description - Chan A / B (Read/Write)
This register enables the Wide mode functionality for the UART.
CUSTOM[0]: Enable wide mode
Logic 0 = Normal (7, 8 or 9 bit data) mode
Logic 1 = Wide mode - “Section 1.5.1.1, Wide Mode Transmit” on page 9, “Section 1.5.2.3, Wide mode
receive operation with 7 or 8-bit data” on page 10 and “Section 1.5.2.4, Wide mode receive operation
with 9-bit data” on page 10.
TABLE 15: UART CUSTOM REGISTERS
ADDRESS
REGISTER NAME
BIT-7
BIT-6
BIT-5
BIT-4
BIT-3
BIT-2
BIT-1
BIT-0
0X03
UART CHAN A CUSTOM
0
MaxPkt-
Size
WIDE_E
N
0X04
UART CHAN A
LOW_LATENCY
0
EN
0X06
UART CHAN A
CUSTOM_INT_PACKET
0
GPIO5
GPIO4
GPIO3
GPIO0
0
GPIO2
GPIO1
0X0B
UART CHAN B CUSTOM
0
MaxPkt-
Size
WIDE_E
N
0X0C
UART CHAN B
LOW_LATENCY
0
EN
0X0E
UART CHAN B
CUSTOM_INT_PACKET
0
GPIO5
GPIO4
GPIO3
GPIO0
0
GPIO2
GPIO1
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