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參數(shù)資料
| 型號： | XR20M1280L24-0B-EB |
| 廠商： | Exar Corporation |
| 文件頁數(shù)： | 61/63頁 |
| 文件大小： | 0K |
| 描述： | EVAL BOARD FOR XR20M128024 |
| 產(chǎn)品培訓(xùn)模塊： | XR21V141x Full-Speed USB UART Family UARTs with Integrated Level Shifters |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 主要目的： | 接口，UART |
| 已用 IC / 零件： | XR20M1280L24 |
| 已供物品： | 板 |
| 其它名稱： | 1016-1631 |
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XR20M1280
7
REV. 1.0.0
I2C/SPI UART WITH 128-BYTE FIFO AND INTEGRATED LEVEL SHIFTERS
1.0 FUNCTIONAL DESCRIPTIONS
1.1
CPU Interface
The XR20M1280 can operate with either an I2C-bus interface or an SPI interface. The CPU interface is
selected via the I2C/SPI# input pin.
1.1.1
I2C-bus Interface
The I2C-bus interface is compliant with the Standard-mode and Fast-mode I2C-bus specifications. The I2C-bus
interface consists of two lines: serial data (SDA) and serial clock (SCL). In the Standard-mode, the serial clock
and serial data can go up to 100 kbps and in the Fast-mode, the serial clock and serial data can go up to 400
kbps. The first byte sent by an I2C-bus master contains a start bit (SDA transition from HIGH to LOW when
SCL is HIGH), 7-bit slave address and whether it is a read or write transaction. The next byte is the sub-
address that contains the address of the register to access. The XR20M1280 responds to each write with an
acknowledge (SDA driven LOW by XR20M1280 for one clock cycle when SCL is HIGH). If the TX FIFO is full,
the XR20M1280 will respond with a negative acknowledge (SDA driven HIGH by XR20M1280 for one clock
cycle when SCL is HIGH) when the CPU tries to write to the TX FIFO. The last byte sent by an I2C-bus master
contains a stop bit (SDA transition from LOW to HIGH when SCL is HIGH). See Figures 3 - 5 below. For
complete details, see the I2C-bus specifications.
FIGURE 3. I C START AND STOP CONDITIONS
SDA
SCL
S
P
START condition
STOP condition
FIGURE 4. MASTER WRITES TO SLAVE (XR20M1280)
SW
A
AP
SLAVE
ADDRESS
REGISTER
ADDRESS
nDATA
White block: host to UART
Grey block: UART to host
FIGURE 5. MASTER READS FROM SLAVE (XR20M1280)
SW
A
AR
SLAVE
ADDRESS
REGISTER
ADDRESS
White block: host to UART
Grey block: UART to host
A
S
SLAVE
ADDRESS
nDATA
ANA
P
LAST DATA
2
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