REV. 1.0.0 I2C/SPI UART WITH 128-BYTE FIFO AND INTEGRATED LEVEL SHIFTERS DLD[7]: BRG select When DLD[6] = 1, this bit selects whet" />
參數(shù)資料
型號： XR20M1280IL32-F
廠商： Exar Corporation
文件頁數(shù)： 40/63頁
文件大?。?/td> 0K
描述： IC UART I2C/SPI 128 BYTE 32QFN
產(chǎn)品培訓模塊： UART Product Overview
XR21V141x Full-Speed USB UART Family
標準包裝： 490
通道數(shù)： 1，UART
FIFO's： 128 字節(jié)
規(guī)程： RS485
電源電壓： 1.62 V ~ 3.63 V
帶自動流量控制功能： 是
帶IrDA 編碼器/解碼器： 是
帶故障啟動位檢測功能： 是
帶調(diào)制解調(diào)器控制功能： 是
安裝類型： 表面貼裝
封裝/外殼： 32-VFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝： 32-QFN 裸露焊盤（5x5）
包裝： 托盤
其它名稱： 1016-1386
XR20M1280
45
REV. 1.0.0
I2C/SPI UART WITH 128-BYTE FIFO AND INTEGRATED LEVEL SHIFTERS
DLD[7]: BRG select
When DLD[6] = 1, this bit selects whether the values written to DLL, DLM and DLD[5:0] will be for the Transmit
Baud Rate Generator or the Receive Baud Rate Generator. When DLD[6] = 0 (same Baud Rate Generator
used for both TX and RX), this bit must be a logic 0 to properly write to the appropriate DLL, DLM and
DLD[5:0].
.
TABLE 18: BRG SELECT
0
Transmitter and Receiver uses same BRG.
Writing to DLL, DLM and DLD[5:0] configures the BRG for both the TX and RX.
0
1
Transmitter and Receiver uses different BRGs.
Writing to DLL, DLM and DLD[5:0] configures the BRG for TX.
1
Transmitter and Receiver uses different BRGs.
Writing to DLL, DLM and DLD[5:0] configures the BRG for RX.
1
0
Transmitter and Receiver uses same BRG.
Writing to DLL, DLM and DLD[5:0] has no effect on BRG used by the TX and RX.
3.16
Trigger Level Register (TRG) - Write-Only
User Programmable Transmit/Receive Trigger Level Register.
TRG[7:0]: Trigger Level Register
These bits are used to program desired trigger levels when trigger Table-D is selected. FCTR bit-7 selects
between programming the RX Trigger Level (a logic 0) and the TX Trigger Level (a logic 1).
3.17
RX/TX FIFO Level Count Register (FC) - Read-Only
This register replaces SPR (during a read) and is accessible when FCTR[6] = 1. This register is also
accessible when LCR = 0xBF. It is suggested to read the FIFO Level Count Register at the Scratchpad
Register location when FCTR bit-6 = 1. See Table 16.
FC[7:0]: RX/TX FIFO Level Count
Receive/Transmit FIFO Level Count. Number of characters in Receiver FIFO (FCTR[7] = 0) or Transmitter
FIFO (FCTR[7] = 1) can be read via this register. Reading this register is OK anytime since setting LCR =
0xBF no longer affects the data byte format.
3.18
Feature Control Register (FCTR) - Read/Write
FCTR[0]: SLEEP/PWRDN# Function Control
Logic 0 = SLEEP pin (input) is enabled. This pin can be used to force the XR20M1280 to enter the sleep
mode immediately after the next data byte that is being transmitted on the TX pin and being received on the
RX pin has been completed.
Logic 1 = PWRDN# pin (output) is enabled. When the XR20M1280 enters the sleep mode, this pin will be
LOW. When the XR20M1280 is not in sleep mode, this pin will be HIGH.
FCTR[1]: Reserved
This bit is reserved and should be ’0’.
FCTR[2]: IrDa RX Inversion
Logic 0 = Select RX input as encoded IrDa data (Idle state will be LOW).
Logic 1 = Select RX input as inverted encoded IrDa data (Idle state will be HIGH).
DLD[7]
DLD[6]
BRG
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