REV. 1.1.0 I2C/SPI UART WITH 64-BYTE FIFO 2.5 Crystal Oscillator or External Clock Input The M1170 includes an on-ch" />
參數(shù)資料
型號(hào)： XR20M1170IL16TR-F
廠商： Exar Corporation
文件頁(yè)數(shù)： 3/56頁(yè)
文件大小： 0K
描述： IC UART FIFO I2C/SPI 64B 16QFN
標(biāo)準(zhǔn)包裝： 3,000
特點(diǎn)： *
通道數(shù)： 1，UART
FIFO's： 64 字節(jié)
規(guī)程： RS485
電源電壓： 2.25 V ~ 3.6 V
帶自動(dòng)流量控制功能： 是
帶IrDA 編碼器/解碼器： 是
帶故障啟動(dòng)位檢測(cè)功能： 是
帶調(diào)制解調(diào)器控制功能： 是
帶CMOS： 是
安裝類型： 表面貼裝
封裝/外殼： 16-VQFN 裸露焊盤(pán)
供應(yīng)商設(shè)備封裝： 16-QFN-EP（4x4）
包裝： 帶卷 (TR)
XR20M1170
11
REV. 1.1.0
I2C/SPI UART WITH 64-BYTE FIFO
2.5
Crystal Oscillator or External Clock Input
The M1170 includes an on-chip oscillator (XTAL1 and XTAL2) to produce a clock for both UART sections in the
device. The crystal oscillator provides a system clock to the Baud Rate Generators (BRG) section found in
each of the UART. XTAL1 is the input to the oscillator or external clock buffer input with XTAL2 pin being the
output. Please note that the input XTAL1 is not 5V tolerant and so the maximum at the pin should be VCC. For
FIGURE 11. TYPICAL OSCILLATOR CONNECTIONS
C1
22-47 pF
C2
22-47 pF
Y1
1.8432 MHz
to
24 MHz
R1
0-120
(Optional)
R2
500Κ1Μ
XTAL1
XTAL2
The on-chip oscillator is designed to use an industry standard microprocessor crystal (parallel resonant,
fundamental frequency with 10-22 pF capacitance load, ESR of 20-120 ohms and 100 ppm frequency
tolerance) connected externally between the XTAL1 and XTAL2 pins (see Figure 11). The programmable
Baud Rate Generator is capable of operating with a crystal oscillator frequency of up to 24 MHz. However, with
an external clock input on XTAL1 pin, it can extend its operation up to 64 MHz (16 Mbps serial data rate) at
3.3V with an 4X sampling rate. For further reading on the oscillator circuit please see the Application Note
DAN108 on the EXAR web site at http://www.exar.com.
2.6
Programmable Baud Rate Generator with Fractional Divisor
Each UART has its own Baud Rate Generator (BRG) with a prescaler for the transmitter and receiver. The
prescaler is controlled by a software bit in the MCR register. The MCR register bit-7 sets the prescaler to divide
the input crystal or external clock by 1 or 4. The output of the prescaler clocks to the BRG. The BRG further
divides this clock by a programmable divisor between 1 and (216 - 0.0625) in increments of 0.0625 (1/16) to
obtain a 16X, 8X or 4X sampling clock of the serial data rate. The sampling clock is used by the transmitter for
data bit shifting and receiver for data sampling. The BRG divisor (DLL, DLM and DLD registers) defaults to the
value of ’1’ (DLL = 0x01, DLM = 0x00 and DLD = 0x00) upon power-up. Therefore, the BRG must be
programmed during initialization to the operating data rate. The DLL and DLM registers provide the integer part
of the divisor and the DLD register provides the fractional part of the dvisior. The four lower bits of the DLD are
used to select a value from 0 (for setting 0000) to 0.9375 or 15/16 (for setting 1111). Programming the Baud
Rate Generator Registers DLL, DLM and DLD provides the capability for selecting the operating data rate.
Table 6 shows the standard data rates available with a 24MHz crystal or external clock at 16X clock rate. If the
pre-scaler is used (MCR bit-7 = 1), the output data rate will be 4 times less than that shown in Table 6. At 8X
sampling rate, these data rates would double and at 4X sampling rate, these data rates would quadruple. Also,
when using 8X sampling mode, the bit time will have a jitter of ± 1/16 whenever the DLD is non-zero and is an
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