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參數資料
| 型號： | XR20M1170IG16 |
| 廠商： | Exar Corporation |
| 文件頁數： | 7/56頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC UART FIFO I2C/SPI 64B 16TSSOP |
| 產品變化通告： | Leaded UART, V&I Obsolescence 11/Apr/2011 |
| 標準包裝： | 95 |
| 特點： | * |
| 通道數： | 1，UART |
| FIFO's： | 64 字節(jié) |
| 規(guī)程： | RS485 |
| 電源電壓： | 2.25 V ~ 3.6 V |
| 帶自動流量控制功能： | 是 |
| 帶IrDA 編碼器/解碼器： | 是 |
| 帶故障啟動位檢測功能： | 是 |
| 帶調制解調器控制功能： | 是 |
| 帶CMOS： | 是 |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-TSSOP（0.173"，4.40mm 寬） |
| 供應商設備封裝： | 16-TSSOP |
| 包裝： | 管件 |
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XR20M1170
15
REV. 1.1.0
I2C/SPI UART WITH 64-BYTE FIFO
2.8
Receiver
The receiver section contains an 8-bit Receive Shift Register (RSR) and 64 bytes of FIFO which includes a
byte-wide Receive Holding Register (RHR). The RSR uses the 16X/8X/4X clock (DLD [5:4]) for timing. It
verifies and validates every bit on the incoming character in the middle of each data bit. On the falling edge of
a start or false start bit, an internal receiver counter starts counting at the 16X/8X/4X clock rate. After 8 clocks
(or 4 if 8X or 2 if 4X) the start bit period should be at the center of the start bit. At this time the start bit is
sampled and if it is still a logic 0 it is validated. Evaluating the start bit in this manner prevents the receiver from
assembling a false character. The rest of the data bits and stop bits are sampled and validated in this same
manner to prevent false framing. If there were any error(s), they are reported in the LSR register bits 2-4. Upon
unloading the receive data byte from RHR, the receive FIFO pointer is bumped and the error tags are
immediately updated to reflect the status of the data byte in RHR register. RHR can generate a receive data
ready interrupt upon receiving a character or delay until it reaches the FIFO trigger level. Furthermore, data
delivery to the host is guaranteed by a receive data ready time-out interrupt when data is not received for 4
word lengths as defined by LCR[1:0] plus 12 bits time. This is equivalent to 3.7-4.6 character times. The RHR
interrupt is enabled by IER bit-0.
2.8.1
Receive Holding Register (RHR) - Read-Only
The Receive Holding Register is an 8-bit register that holds a receive data byte from the Receive Shift
Register. It provides the receive data interface to the host processor. The RHR register is part of the receive
FIFO of 64 bytes by 11-bits wide, the 3 extra bits are for the 3 error tags to be reported in LSR register. When
the FIFO is enabled by FCR bit-0, the RHR contains the first data character received by the FIFO. After the
RHR is read, the next character byte is loaded into the RHR and the errors associated with the current data
byte are immediately updated in the LSR bits 2-4.
FIGURE 15. RECEIVER OPERATION IN NON-FIFO MODE
R eceive D ata Shift
R egister (R SR)
Receive
D ata Byte
and Errors
R H R Interrupt (ISR bit-2)
Receive Data
H olding R egister
(R H R)
R XFIFO 1
16X or 8X or 4X C lock
( D LD[5:4] )
R eceive Data Characters
D ata Bit
Validation
Error
Tags in
LSR bits
4:2
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相關代理商/技術參數 |
參數描述 |
|---|---|
| XR20M1170IG16-F | 功能描述:UART 接口集成電路 UART RoHS:否 制造商:Texas Instruments 通道數量:2 數據速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel |
| XR20M1170IG16-F | 制造商:Exar Corporation 功能描述:IC SGL UART 16MBPS 3.63V 16-TSSOP 制造商:Exar Corporation 功能描述:IC, SGL UART, 16MBPS, 3.63V, 16-TSSOP |
| XR20M1170IG16TR-F | 制造商:Exar Corporation 功能描述:UART 1-CH 64Byte FIFO 1.8V/2.5V/3.3V 16-Pin TSSOP T/R 制造商:Exar Corporation 功能描述:XR20M1170IG16TR-F 制造商:EXAR 功能描述:UART 1-CH 64Byte FIFO 1.8V/2.5V/3.3V 16-Pin TSSOP T/R |
| XR20M1170IG24 | 功能描述:UART 接口集成電路 UART RoHS:否 制造商:Texas Instruments 通道數量:2 數據速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel |
| XR20M1170IG24-F | 功能描述:UART 接口集成電路 UART RoHS:否 制造商:Texas Instruments 通道數量:2 數據速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel |
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