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參數(shù)資料
型號(hào)： XR19L200IL32-0B-EB
廠商： Exar Corporation
文件頁(yè)數(shù)： 23/40頁(yè)
文件大小： 0K
描述： EVAL BOARD FOR XR19L200 32QFN
標(biāo)準(zhǔn)包裝： 1
系列： *
XR19L200
3
REV. 1.0.2
SINGLE CHANNEL INTEGRATED UART AND RS-232 TRANSCEIVER
PIN DESCRIPTIONS
Pin Descriptions
NAME
32-QFN
PIN#
TYPE
DESCRIPTION
DATA BUS INTERFACE (CMOS/TTL Voltage Levels)
A2
A1
A0
18
19
20
I
Address bus lines [2:0]. These 3 address lines select one of the internal registers in the
UART during a data bus transaction.
D7
D6
D5
D4
D3
D2
D1
D0
6
5
3
32
31
30
29
28
I/O
Data bus lines [7:0] (bidirectional).
IOR#
(NC)
14
I
When I/M# pin is HIGH, the Intel bus interface is selected and this input becomes read
strobe (active LOW). The falling edge instigates an internal read cycle and retrieves the
data byte from an internal register pointed by the address lines [A2:A0], puts the data byte
on the data bus to allow the host processor to read it on the rising edge.
When I/M# pin is LOW, the Motorola bus interface is selected and this input is not used.
IOW#
(R/W#)
11
I
When I/M# pin is HIGH, it selects Intel bus interface and this input becomes write strobe
(active LOW). The falling edge instigates the internal write cycle and the rising edge trans-
fers the data byte on the data bus to an internal register pointed by the address lines.
When I/M# pin is LOW, the Motorola bus interface is selected and this input becomes read
(HIGH) and write (LOW) signal.
CS#
7
I
This input is chip select (active LOW) to enable the device.
INT
(IRQ#)
21
O
(OD)
When I/M# pin is HIGH, it selects Intel bus interface and this output become the active
HIGH device interrupt output. This output is enabled through the software setting of MCR[3]:
set to the active mode when MCR[3] is set to a logic 1, and set to the three state mode when
MCR[3] is set to a logic 0. See MCR[3].
When I/M# pin is LOW, it selects Motorola bus interface and this output becomes the active
LOW, open-drain interrupt output. An external pull-up resistor is required for proper opera-
tion. MCR[3] must be set to a logic 0 for proper operation of the interrupt.
MODEM OR SERIAL I/O INTERFACE (EIA-232/RS-232 Voltage Levels)
TXD
8
O
UART Transmit Data. The TX signal will be LOW (< -5V) during reset or idle (no data).
RXD
1
I
UART Receive Data. The RX data input must idle LOW (< -3V).
ANCILLARY SIGNALS (CMOS/TTL Voltage Levels)
XTAL1
9
I
Crystal or external clock input. This input is not 5V tolerant.
XTAL2
10
O
Crystal or buffered clock output. This output may be use to drive a clock buffer which can
drive other device(s).
ACP
12
I
Autosleep for Charge Pump (active HIGH). When this pin is HIGH, the charge pump is shut
off if the L200 is already in partial sleep mode, i.e. the crystal oscillator is stopped.
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