REV. 1.0.3 HIGH PERFORMANCE QUAD PCI-EXPRESS UART 8X sampling rate. Transmit and receive data rates will double by selecting 8X. If" />
參數(shù)資料
型號: XR17V354IB176-F
廠商: Exar Corporation
文件頁數(shù): 16/66頁
文件大小: 0K
描述: IC UART PCIE 256B QUAD 176FPBGA
產(chǎn)品培訓(xùn)模塊: PCIe UARTs
標(biāo)準(zhǔn)包裝: 160
特點: *
通道數(shù): 4,QUART
FIFO's: 256 字節(jié)
規(guī)程: RS485
電源電壓: 3.3V
帶自動流量控制功能:
帶IrDA 編碼器/解碼器:
帶故障啟動位檢測功能:
帶調(diào)制解調(diào)器控制功能:
安裝類型: 表面貼裝
封裝/外殼: 176-LFBGA
供應(yīng)商設(shè)備封裝: 176-FPBGA(13x13)
包裝: 托盤
其它名稱: 1016-1472
XR17V354IB176-F-ND
XR17V354
23
REV. 1.0.3
HIGH PERFORMANCE QUAD PCI-EXPRESS UART
8X sampling rate. Transmit and receive data rates will double by selecting 8X. If using the 4XMODE, the
corresponding bit in this register should be logic 0
0
Ch-3 Ch-2 Ch-1 Ch-0
8XMODE Register
Individual UART Channel 8X Clock Mode Enable
Bit-7 Bit-6 Bit-5 Bit-4 Bit-3 Bit-2 Bit-1 Bit-0
1.4.4
4XMODE [15:8] (default 0x00)
Each bit selects 4X or 16X sampling rate for that UART channel. The 4XMODE register is accessible from the
Device Configuration Registers in all UART channels but the UART channel can only control the bit for that
channel. For example, bit [0] is channel 0 and can only be controlled by channel 0. All other bits are read-only
in channel 0. Logic 0 (default) selects normal 16X sampling (and 8XMODE = 0x00) with logic one selects 4X
sampling rate. Transmit and receive data rates will quadruple by selecting 4X. If using the 8XMODE, the
corresponding bit in this register should be logic 0
0
Ch-3 Ch-2 Ch-1 Ch-0
4XMODE Register
Individual UART Channel 4X Clock Mode Enable
Bit-7 Bit-6 Bit-5 Bit-4 Bit-3 Bit-2 Bit-1 Bit-0
RESET [23:16] (default 0x00)
The 8-bit RESET register provides the software with the ability to reset the UART(s) when there is a need. The
RESET register is accessible from the Device Configuration Registers in all UART channels but the UART
channel can only control the bit for that channel. For example, writing 0xFF to the RESET register in channel 0
will only reset channel 0. Each bit is self-clearing after it is written a logic 1 to perform a reset to that channel.
All registers in that channel will be reset to the default condition, see Table 21 for details. .
0
Ch-3 Ch-2 Ch-1 Ch-0
RESET Register
Individual UART Channel Reset Enable
Bit-7 Bit-6 Bit-5 Bit-4 Bit-3 Bit-2 Bit-1 Bit-0
1.4.5
SLEEP [31:24] (default 0x00)
SLEEP Register
Individual UART Channel Sleep Enable
Bit-6
Bit-7
Bit-5 Bit-4 Bit-3 Bit-2 Bit-1 Bit-0
0
Ch-3 Ch-2 Ch-1 Ch-0
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