參數(shù)資料
型號(hào): XR17V254IV-F
廠商: Exar Corporation
文件頁(yè)數(shù): 17/70頁(yè)
文件大?。?/td> 0K
描述: IC UART PCI BUS QUAD 144LQFP
標(biāo)準(zhǔn)包裝: 60
特點(diǎn): *
通道數(shù): 4,QUART
FIFO's: 64 字節(jié)
規(guī)程: RS485
電源電壓: 3.3V,5V
帶自動(dòng)流量控制功能:
帶IrDA 編碼器/解碼器:
帶故障啟動(dòng)位檢測(cè)功能:
帶調(diào)制解調(diào)器控制功能:
安裝類型: 表面貼裝
封裝/外殼: 144-LQFP
供應(yīng)商設(shè)備封裝: 144-LQFP(20x20)
包裝: 托盤
XR17V254
24
66MHZ PCI BUS QUAD UART WITH POWER MANAGEMENT SUPPORT
REV. 1.0.1
MPIOINT [7:0] (default 0x00)
Enable multipurpose input pin interrupt. If the pin is selected by MPIOSEL as input then bit [0] enables input
pin 0 for interrupt, and bit [7] enables input pin 7. No interrupt is enable if the pin is selected to be an output.
The interrupt is edge sensing and determined by MPIOINV and MPIOLVL registers. The MPIO interrupt clears
after a read to register MPIOLVL. The combination of MPIOLVL and MPIOINV determines the interrupt being
active LOW or active high, it’s level trigger. Logic LOW (default) disables the pin’s interrupt and logic HIGH
enables it.
MPIOLVL [7:0] (default 0x00)
Output pin level control and input level status. The status of the input pin(s) is read on this register and output
pins are controlled on this register. A logic 0 (default) sets the output to LOW and a logic 1 sets the output pin
to HIGH. The MPIO interrupt will clear upon reading this register.
FIGURE 9. MULTIPURPOSE INPUT/OUTPUT INTERNAL CIRCUIT
MPIO
Pin [7:0]
MPIOLVL [7:0]
Read Input Level
MPIOINT [7:0]
Rising Edge
Detection
INT
OR
AND
1
0
MPIOSEL [7:0]
(Select Input=1, Output=0 )
MPIO3T [7:0]
(3-state Enable =1)
MPIOLVL [7:0]
(Output Level)
MPIOINV [7:0]
(Input Inversion Enable =1)
MPIOCKT
MPIO6
MPIO7
MPIO5 MPIO4 MPIO3 MPIO2 MPIO1 MPIO0
MPIOINT Register
Multipurpose Input/Output Interrupt Enable
Bit-7 Bit-6 Bit-5 Bit-4 Bit-3 Bit-2 Bit-1 Bit-0
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