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參數(shù)資料
| 型號： | XR17V252IM |
| 廠商： | Exar Corporation |
| 文件頁數(shù)： | 18/69頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC UART PCI BUS DUAL 100TQFP |
| 產(chǎn)品變化通告： | Leaded UART, V&I Obsolescence 11/Apr/2011 |
| 標準包裝： | 90 |
| 特點： | * |
| 通道數(shù)： | 2，DUART |
| FIFO's： | 64 字節(jié) |
| 規(guī)程： | RS485 |
| 電源電壓： | 3.3V，5V |
| 帶自動流量控制功能： | 是 |
| 帶IrDA 編碼器/解碼器： | 是 |
| 帶故障啟動位檢測功能： | 是 |
| 帶調(diào)制解調(diào)器控制功能： | 是 |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 100-TQFP |
| 供應(yīng)商設(shè)備封裝： | 100-TQFP（14x14） |
| 包裝： | 托盤 |
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XR17V252
25
REV. 1.0.2
66 MHZ PCI BUS DUAL UART WITH POWER MANAGEMENT SUPPORT
3.0
TRANSMIT AND RECEIVE DATA
There are two methods to load transmit data and unload receive data from each UART channel. First, there is
a transmit data register and receive data register for each UART channel as shown in Table 5 set to ease
programming. These registers support 8, 16, 24 and 32 bits wide format. In the 32-bit format, it increases the
data transfer rate on the PCI bus. Additionally, a special register location provides receive data byte with its
associated error flags. This is a 16-bit or 32-bit read operation where the Line Status Register (LSR) content in
the UART channel register is paired along with the data byte. This operation further facilitates data unloading
with the error flags without having to read the LSR register separately. Furthermore, the XR17V252 supports
PCI burst mode for read/write operation of up to 64 bytes of data.
The second method is through each UART channel’s transmit holding register (THR) and receive holding
register (RHR). The THR and RHR registers are 16550 compatible so their access is limited to 8-bit format.
The software driver must separately read the LSR content for the associated error flags before reading the
data byte.
3.1
FIFO DATA LOADING AND UNLOADING IN 32-BIT FORMAT
The XR17V252 supports PCI Burst Read and PCI Burst Write transactions anywhere in the mapped memory
region (except reserved areas). In addition, to utilize this feature fully, the device provides a separate memory
location (apart from the individual channel’s register set) where the RX and the TX FIFO can be read from/
written to, as shown in Table 5. The following is an extract from the table showing the burstable memory
locations:
Channel 0:
RX FIFO
:
0x100 - 0x13F (64 bytes)
TX FIFO
:
0x100 - 0x13F (64 bytes)
RX FIFO + status
:
0x180 - 0x1FF (64 bytes data + 64 bytes status)
Channel 1:
RX FIFO
:
0x300 - 0x33F (64 bytes)
TX FIFO
:
0x300 - 0x33F (64 bytes)
RX FIFO + status
:
0x380 - 0x3FF (64 bytes data + 64 bytes status)
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| XR17V252IM-0A-EVB | 功能描述:UART 接口集成電路 Supports V252 100 ld TQFP, PCI Interface RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel |
| XR17V252IM-F | 功能描述:UART 接口集成電路 66MHz Dual PCI UART RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel |
| XR17V252IMTR-F | 制造商:Exar Corporation 功能描述:UART 2-CH 64Byte FIFO 3.3V 100-Pin TQFP T/R 制造商:Exar Corporation 功能描述:XR17V252IMTR-F |
| XR17V254 | 制造商:EXAR 制造商全稱:EXAR 功能描述:66MHZ PCI BUS QUAD UART WITH POWER MANAGEMENT SUPPORT |
| XR17V254_08 | 制造商:EXAR 制造商全稱:EXAR 功能描述:66MHZ PCI BUS QUAD UART WITH POWER MANAGEMENT SUPPORT |
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