參數(shù)資料
型號: XR17L154CV
元件分類: 通信、網(wǎng)絡(luò)模塊及開發(fā)工具
英文描述: Telecomm/Datacomm
中文描述: 電信/數(shù)據(jù)通信
文件頁數(shù): 1/58頁
文件大?。?/td> 676K
代理商: XR17L154CV
Exar
Corporation 48720 Kato Road, Fremont CA, 94538
(510) 668-7000
FAX (510) 668-7017
www.exar.com
á
XR17L154
3.3V PCI BUS QUAD UART
OCTOBER 2002
REV. 1.0.0
GENERAL DESCRIPTION
The XR17L154
1
(L154) is a quad PCI Bus Universal
Asynchronous Receiver and Transmitter (UART) with
same package and pin-out as the Exar XR17C158
octal UART. The device is designed to meet today’s
32-bit PCI Bus and high bandwidth requirement in
communication systems. The global interrupt source
register provides a complete interrupt status
indication for all 4 channels to speed up interrupt
parsing. Each UART is independently controlled and
has its own 16C550 compatible 5G register set,
transmit and receive FIFOs of 64 bytes, fully
programmable transmit and receive FIFO trigger
levels, transmit and receive FIFO level counters,
automatic hardware flow control with programmable
hysteresis, automatic software (Xon/Xoff) flow
control, IrDA (Infrared Data Association) encoder/
decoder, 8 multi-purpose definable inputs/outputs,
and a 16-bit general purpose timer/counter.
N
OTE
:
1 Covered by U.S. Patents #5,649,122, #5,832,205
APPLICATIONS
Remote Access Servers
Ethernet Network to Serial Ports
Network Management
Factory Automation and Process Control
Point-of-Sale Systems
Multi-port RS-232/RS-422/RS-485 Cards
FEATURES
High Performance Quad UART
PCI Bus 2.2 Target Interface Compliance
3.3 Volt PCI Bus Compliant up to 33 MHz Clock
5 Volt Tolerant Serial Inputs
32-bit PCI Bus Interface with EEPROM Interface
A Global Interrupt Source Register for all 4 UARTs
Data Transfer in Byte, Word and Double-word
Data Read/Write Burst Operation
Each UART is independently Controlled with:
16C550 Compatible 5G (Fifth Gen) Register Set
64-byte Transmit and Receive FIFOs
Transmit and Receive FIFO Level Counters
Automatic RTS/CTS or DTR/DSR Flow Control
Automatic Xon/Xoff Software Flow Control
Automatic RS485 Half-duplex Control Output with
Selectable Turn-around Delay (0 to 15 bit-times)
Infrared (IrDA 1.0) Data Encoder/Decoder
Programmable Data Rate with Prescaler
Up to 4 Mbps Serial Data Rate at 8X
Eight Multi-Purpose Inputs/outputs
General Purpose 16-bit Timer/Counter
Sleep Mode with Automatic Wake-up
Same Package and Pin-out as XR17C158 and
XR17C154 UARTs (20x20x1.4mm 144-TQFP)
F
IGURE
1. B
LOCK
D
IAGRAM
TMRCK
Device
Configuration
Registers
XTAL1
XTAL2
Crystal Osc/Buffer
UART Channel 0
TX0, RX0, DTR0#,
DSR0#, RTS0#,
CTS0#, CD0#, RI0#
PCI Local
Bus
Interface
CLK (33MHz)
RST#
AD[31:0]
C/BE[3:0]#
FRAME#
IRDY#
TRDY#
DEVSEL#
STOP#
INTA#
PAR
IDSEL
PERR#
SERR#
Configuration
Space
Registers
MPIO0- MPIO7
Multi-pu.
Inputs/Outputs
TX3, RX3, DTR3#,
DSR3#, RTS3#,
CTS3#, CD3#, RI3#
UART Channel 3
UART Channel 2
UART Channel 1
16-bit
Timer/Counter
EECK
EEPROM
Interface
64 Byte TX FIFO
64 Byte RX FIFO
BRG
IR
ENDEC
TX & RX
UART
Regs
3.3V VCC
GND
*5V Tolerance for non-PCI Inputs
ENIR
相關(guān)PDF資料
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