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參數(shù)資料
| 型號： | XR17L152 |
| 廠商： | Exar Corporation |
| 英文描述： | 3.3V PCI BUS DUAL UART |
| 中文描述： | 3.3V的PCI總線雙UART |
| 文件頁數(shù)： | 20/55頁 |
| 文件大?。?/td> | 318K |
| 代理商： | XR17L152 |
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DISCONTINUED
XR17L152
3.3V PCI BUS DUAL UART
REV. 1.1.0
20
Each Channel Special Receive FIFO Data Address for channel 0 and 1 are at 0x0180 and 0x380. The Status
and Data bytes must be read in 16 or 32 bits format to maintain data integrity.
3.2
FIFO
DATA LOADING AND UNLOADING THROUGH THE UART CHANNEL REGISTERS, THR
AND RHR IN 8-BIT FORMAT
The THR and RHR register address for channel 0 to channel 1 is shown in
Table 8
below. The THR and RHR
for each channel 0 tand 1 are located sequentially at address 0x0000 and 0x0200. Transmit data byte is loaded
to the THR when writing to that address and receive data is unloaded from the RHR register when reading that
address. Both THR and RHR registers are 16C550 compatible in 8-bit format, so each bus operation can only
write or read in bytes.
4.0
UART
There are 2 UARTs [channels 1:0] n the L152. Each has its own 64-byte of transmit and receive FIFO, a set of
16550 compatible control and status registers, and a baud rate generator for individual channel data rate
setting. Eight additional registers per UART were added for the EXAR enhanced features.
R
EAD
RX FIFO,
WITH
LSR
E
RRORS
B
YTE
3
B
YTE
2
B
YTE
1
B
YTE
0
Read n+0 to n+1
FIFO Data n+1
LSR n+1
FIFO Data n+0
LSR n+0
Read n+2 to n+3
FIFO Data n+3
LSR n+3
FIFO Data n+2
LSR n+2
Etc
T
ABLE
8: T
RANSMIT
AND
R
ECEIVE
D
ATA
R
EGISTER
IN
B
YTE
FORMAT
, 16C550
COMPATIBLE
PCI Bus
Data Bit-31
B7
B6
B5
B4
B3
B2
B1
B0
B7
B6
B5
B4
B3
B2
B1
B0
B7
B6
B5
B4
B3
B2
B1
B0
B7
B6
B5
B4
B3
B2
B1
B0
Receive Data Byte n+1
Line Status Register n+1
Receive Data Byte n+0
Line Status Register n+0
PCI Bus
Data Bit-0
Channel 0 to 1 Receive Data with Line Status Register in a 32-bit alignment through
the Configuration Register Address 0x0180 and 0x0380
THR and RHR Address Locations For CH0 to CH1 (16C550 Compatible)
CH0 0x000 Write THR
CH0 0x000 Read RHR
CH1 0x200 Write THR
CH1 0x200 Read RHR
Bit-7
Bit-6
Bit-5
Bit-4
Bit-3
Bit-2
Bit-1
Bit-0
Bit-7
Bit-6
Bit-5
Bit-4
Bit-3
Bit-2
Bit-1
Bit-0
Bit-7
Bit-6
Bit-5
Bit-4
Bit-3
Bit-2
Bit-1
Bit-0
Bit-7
Bit-6
Bit-5
Bit-4
Bit-3
Bit-2
Bit-1
Bit-0
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| XR17L152CM | 3.3V PCI BUS DUAL UART |
| XR2001 | High-Voltage, High-Current Darlington Transistor Arrays |
| XR2002CN | High-Voltage, High-Current Darlington Transistor Arrays |
| XR2003 | High-Voltage, High-Current Darlington Transistor Arrays |
| XR2003CN | Programable Driver IC |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| XR17L152CM | 制造商:EXAR 制造商全稱:EXAR 功能描述:3.3V PCI BUS DUAL UART |
| XR17L152IM | 制造商:EXAR 制造商全稱:EXAR 功能描述:3.3V PCI BUS DUAL UART |
| XR17L154 | 制造商:EXAR 制造商全稱:EXAR 功能描述:3.3V PCI BUS QUAD UART |
| XR17L154CV | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Telecomm/Datacomm |
| XR17L154IV | 制造商:EXAR 制造商全稱:EXAR 功能描述:3.3V PCI BUS QUAD UART |
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