REV. 1.2.2 UNIVERSAL (3.3V AND 5V) PCI BUS OCTAL UART 3 PIN DESCRIPTIONS NAME
參數(shù)資料
型號(hào)： XR17D158IV
廠商： Exar Corporation
文件頁(yè)數(shù)： 23/73頁(yè)
文件大小： 0K
描述： IC UART PCI BUS OCTAL 144LQFP
產(chǎn)品變化通告： Leaded UART, V&I Obsolescence 11/Apr/2011
標(biāo)準(zhǔn)包裝： 60
特點(diǎn)： *
通道數(shù)： 8
FIFO's： 64 字節(jié)
規(guī)程： RS485
電源電壓： 3.3V，5V
帶自動(dòng)流量控制功能： 是
帶IrDA 編碼器/解碼器： 是
帶故障啟動(dòng)位檢測(cè)功能： 是
帶調(diào)制解調(diào)器控制功能： 是
安裝類(lèi)型： 表面貼裝
封裝/外殼： 144-LQFP
供應(yīng)商設(shè)備封裝： 144-LQFP（20x20）
包裝： 托盤(pán)
xr
XR17D158
REV. 1.2.2
UNIVERSAL (3.3V AND 5V) PCI BUS OCTAL UART
3
PIN DESCRIPTIONS
NAME
PIN #
TYPE
DESCRIPTION
PCI LOCAL BUS INTERFACE
RST#
134
I
PCI bus reset input (active low). It resets the PCI local bus configuration
space registers, device configuration registers and UART channel registers to
the default condition.
CLK
135
I
PCI bus clock input of up to 33.34MHz.
AD31-AD25,
AD24,
AD23-AD16,
AD15-AD8,
AD7-AD0
138-144,
1,
6-13,
26-33,
37-44
IO
Address data lines [31:0] (bidirectional).
FRAME#
15
I
Bus transaction cycle frame (active low). It indicates the beginning and dura-
tion of an access.
C/BE0#-
C/BE3#
36,25,14,2
I
Bus Command/Byte Enable [3:0] (active low). This line is multiplexed for bus
Command during the address phase and Byte Enables during the data
phase.
IRDY#
16
I
Initiator Ready (active low). During a write, it indicates that valid data is
present on data bus. During a read, it indicates the master is ready to accept
data.
TRDY#
17
O
Target Ready (active low).
STOP#
21
O
Target request to stop current transaction (active low).
IDSEL
3
I
Initialization device select (active high).
DEVSEL#
18
O
Device select to the XR17D158 (active low).
INTA#
133
OD
Device interrupt from XR17D158 (open drain, active low).
PAR
24
IO
Parity is even across AD[31:0] and C/BE[3:0]# (bidirectional, active high).
PERR#
22
O
Data Parity error indicator, except for Special Cycle transactions (active low).
Optional in bus target application.
SERR#
23
OD
System error indicator, Address parity or Data parity during Special Cycle
transactions (open drain, active low). Optional in bus target application.
MODEM OR SERIAL I/O INTERFACE
TX0
125
O
UART channel 0 Transmit Data or infrared transmit data. Normal TXD output
idles HIGH while infrared TXD output idles LOW.
RX0
132
I
UART channel 0 Receive Data or infrared receive data. Normal RXD input
idles HIGH. The infrared pulses typically idle LOW but can be inverted inter-
nally prior the decoder by FCTR[4].
RTS0#
127
O
UART channel 0 Request to Send or general purpose output (active low).
CTS0#
131
I
UART channel 0 Clear to Send or general purpose input (active low).
DTR0#
126
O
UART channel 0 Data Terminal Ready or general purpose output (active low).
DSR0#
130
I
UART channel 0 Data Set Ready or general purpose input (active low).
CD0#
129
I
UART channel 0 Carrier Detect or general purpose input (active low).
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