REV. 1.2.2 44 FCR[2]: TX FIFO Reset This bit is only active when FCR bit-0 is active. L" />
參數(shù)資料
型號: XR17D158IV-F
廠商: Exar Corporation
文件頁數(shù): 39/73頁
文件大小: 0K
描述: IC UART PCI BUS OCTAL 144LQFP
產(chǎn)品培訓模塊: UART Product Overview
標準包裝: 60
特點: *
通道數(shù): 8
FIFO's: 64 字節(jié)
規(guī)程: RS485
電源電壓: 3.3V,5V
帶自動流量控制功能:
帶IrDA 編碼器/解碼器:
帶故障啟動位檢測功能:
帶調制解調器控制功能:
安裝類型: 表面貼裝
封裝/外殼: 144-LQFP
供應商設備封裝: 144-LQFP(20x20)
包裝: 托盤
其它名稱: 1016-1292
XR17D158
xr
UNIVERSAL (3.3V AND 5V) PCI BUS OCTAL UART
REV. 1.2.2
44
FCR[2]: TX FIFO Reset
This bit is only active when FCR bit-0 is active.
Logic 0 = No transmit FIFO reset (default).
Logic 1 = Reset the transmit FIFO pointers and FIFO level counter logic (the transmit shift register is not
cleared or altered). This bit will return to a logic 0 after resetting the FIFO.
FCR[3]: DMA Mode Select
This bit has no effect since TXRDY and RXRDY pins are not available in this device. It is provided for legacy
software. DMA is a legacy term used for block transfer mode. DMA does not stand for "Direct Memory Ac-
cess."
Logic 0 = Set DMA to mode 0 (default).
Logic 1 = Set DMA to mode 1.
FCR[5:4]: Transmit FIFO Trigger Select
(logic 0 = default, TX trigger level = 1)
The FCTR bits 6-7 are associated with these 2 bits by selecting one of the four tables. The 4 user selectable
trigger levels in 4 tables are supported for compatibility reasons. These 2 bits set the trigger level for the
transmit FIFO interrupt. The UART will issue a transmit interrupt when the number of characters in the FIFO
falls below the selected trigger level, or when it gets empty in case that the FIFO did not get filled over the
trigger level on last re-load. Table 15 below shows the selections. EFR bit-4 must be set to ‘1’ before these
bits can be accessed. Note that the receiver and the transmitter cannot use different trigger tables. Whichever
selection is made last applies to both the RX and TX side.
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