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參數(shù)資料
型號(hào)： XR17D152IM-F
廠商： Exar Corporation
文件頁(yè)數(shù)： 7/68頁(yè)
文件大?。?/td> 0K
描述： IC UART PCI BUS DUAL 100TQFP
標(biāo)準(zhǔn)包裝： 90
特點(diǎn)： *
通道數(shù)： 2，DUART
FIFO's： 64 字節(jié)
規(guī)程： RS485
電源電壓： 3.3V，5V
帶自動(dòng)流量控制功能： 是
帶IrDA 編碼器/解碼器： 是
帶故障啟動(dòng)位檢測(cè)功能： 是
帶調(diào)制解調(diào)器控制功能： 是
安裝類型： 表面貼裝
封裝/外殼： 100-TQFP
供應(yīng)商設(shè)備封裝： 100-TQFP（14x14）
包裝： 托盤
其它名稱： XR17D152IM-F-ND
á
XR17D152
REV. 1.2.0
UNIVERSAL (3.3V AND 5V) PCI BUS DUAL UART
15
.
FIGURE 6. THE GLOBAL INTERRUPT REGISTER, INT0, INT1, INT2 AND INT3
TABLE 5: UART CHANNEL [1:0] INTERRUPT SOURCE ENCODING
PRIORITY
BIT[N+2]
BIT[N+1]
BIT[N]
INTERRUPT SOURCE(S)
x
000
None
1001
RXRDY and RX Line Status (logic OR of LSR[4:1])
2010
RXRDY Time-out
3011
TXRDY, THR or TSR (auto RS485 mode) empty
4100
MSR, RTS/CTS or DTR/DSR delta or Xoff/Xon det. or special char. detected
5101
Reserved.
6110
MPIO pin(s). Available only in channel 0, reserved in channel 1.
7111
TIMER Time-out. Available only in channel 0, reserved channel 1.
TABLE 6: UART CHANNEL [1:0] INTERRUPT CLEARING:
RXRDY is cleared by reading data in the RX FIFO until it falls below the trigger level.
RXRDY Time-out is cleared by reading data until the RX FIFO is empty.
RX Line Status interrupt clears after reading the LSR register.
TXRDY interrupt clears after reading ISR register that is in the UART channel register set.
Modem Status Register interrupt clears after reading MSR register that is in the UART channel register set.
RTS/CTS or DTR/DSR delta interrupt clears after reading MSR register that is in the UART channel register set.
Xoff/Xon interrupt clears after reading the ISR register that is in the UART channel register set.
Special character detect interrupt is cleared by a read to ISR or after the next character is received.
TIMER Time-out interrupt clears after reading the TIMERCNTL register that is in the Device Configuration register set.
MPIO interrupt clears after reading the MPIOLVL register that is in the Device Configuration register set.
Rsvd
Channel-1
Channel-0
INT2 Register
INT1 Register
INT3 Register
INT0 Register
Interrupt Registers,
INT0, INT1, INT2 and INT3
Bit-0
Bit-1
Bit-2
Bit-3
Bit-7
Bit-4
Bit-5
Bit-6
Rsvd
Rsvd Ch-1 Ch-0
Bit
N+1
Bit
N+2
Bit
N
Bit
N+1
Bit
N+2
Bit
N
Bit
N+1
Bit
N+2
Bit
N
Bit
N+1
Bit
N+2
Bit
N
Bit
N+1
Bit
N+2
Bit
N
Bit
N+1
Bit
N+2
Bit
N
Bit
N+1
Bit
N+2
Bit
N
Bit
N+1
Bit
N+2
Bit
N
Rsvd
Rsvd Rsvd
Rsvd
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