XR16V654/654D
5
REV. 1.0.1
2.25V TO 3.6V QUAD UART WITH 64-BYTE FIFO
PIN DESCRIPTIONS
ORDERING INFORMATION
PART NUMBER
PACKAGE
OPERATING TEMPERATURE
RANGE
DEVICE STATUS
XR16V654IJ
68-Lead PLCC
-40°C to +85°C
Active
XR16V654IV
64-Lead LQFP
-40°C to +85°C
Active
XR16V654DIV
64-Lead LQFP
-40°C to +85°C
Active
XR16V654IQ
100-Lead QFP
-40°C to +85°C
Active
XR16V654IL
48-pin QFN
-40°C to +85°C
Active
XR16V654IV80
80-Lead LQFP
-40°C to +85°C
Active
Pin Description
NAME
48-QFN
PIN #
64-LQFP
PIN #
68-PLCC
PIN#
80-LQFP
PIN #
100-QFP
PIN #
TYPE
DESCRIPTION
DATA BUS INTERFACE
A2
A1
A0
15
16
17
22
23
24
32
33
34
28
29
30
37
38
39
I
Address data lines [2:0]. These 3 address
lines select one of the internal registers in
UART channel A-D during a data bus trans-
action.
D7
D6
D5
D4
D3
D2
D1
D0
46
45
44
43
42
41
40
39
60
59
58
57
56
55
54
53
5
4
3
2
1
68
67
66
75
74
73
72
71
70
69
68
95
94
93
92
91
90
89
88
I/O
Data bus lines [7:0] (bidirectional).
IOR#
(VCC)
29
40
52
51
66
I
When 16/68# pin is HIGH, the Intel bus
interface is selected and this input becomes
read strobe (active low). The falling edge
instigates an internal read cycle and
retrieves the data byte from an internal reg-
ister pointed by the address lines [A2:A0],
puts the data byte on the data bus to allow
the host processor to read it on the rising
edge.
When 16/68# pin is LOW, the Motorola bus
interface is selected and this input is not
used and should be connected to VCC.