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參數(shù)資料
| 型號(hào)： | XR16V598IQ100-F |
| 廠商： | Exar Corporation |
| 文件頁數(shù)： | 8/58頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC UART FIFO 16B OCTAL 100QFP |
| 標(biāo)準(zhǔn)包裝： | 66 |
| 特點(diǎn)： | * |
| 通道數(shù)： | 8 |
| FIFO's： | 16 字節(jié) |
| 規(guī)程： | RS485 |
| 電源電壓： | 2.25 V ~ 3.6 V |
| 帶自動(dòng)流量控制功能： | 是 |
| 帶IrDA 編碼器/解碼器： | 是 |
| 帶故障啟動(dòng)位檢測功能： | 是 |
| 帶調(diào)制解調(diào)器控制功能： | 是 |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 100-BQFP |
| 供應(yīng)商設(shè)備封裝： | 100-QFP（14x20） |
| 包裝： | 托盤 |
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XR16V598
16
2.25V TO 3.6V HIGH PERFORMANCE OCTAL UART WITH 16-BYTE FIFO
REV. 1.0.3
2.11
Auto Xon/Xoff (Software) Flow Control
When software flow control is enabled (See Table 17), the 598 compares one or two sequential receive data
characters with the programmed Xon-1,2 or Xoff-1,2 character value(s). If receive character(s) (RX) match the
programmed Xoff-1,2 value(s), the 598 will halt transmission (TX) as soon as the current character has
completed transmission. When a match occurs, the Xoff (if enabled via IER bit-5) flag will be set and the
interrupt output pin will be activated. Following a suspension due to a match of the Xoff character(s), the 598
will monitor the receive data stream for a match to the Xon-1,2 character(s). If a match is found, the 598 will
resume operation and clear the flags (ISR bit-4).
Reset initially sets the contents of the Xon1, Xon2, Xoff1 and Xoff2 flow control registers to ’0’. Following reset,
any desired Xon/Xoff value can be used for software flow control. Different conditions can be set to detect Xon/
Xoff characters (See Table 17) and suspend/resume transmissions. When double 8-bit Xon/Xoff characters
are selected, the 598 compares two consecutive receive characters with two software flow control 8-bit values
FIGURE 9. AUTO RTS/DTR AND CTS/DSR FLOW CONTROL OPERATION
The local UART (UARTA) starts data transfer by asserting RTSA# (1). RTSA# is normally connected to CTSB# (2) of
remote UART (UARTB). CTSB# allows its transmitter to send data (3). TXB data arrives and fills UARTA receive FIFO
(4). When RXA data fills up to its receive FIFO trigger level, UARTA activates its RXA data ready interrupt (5) and con-
tinues to receive and put data into its FIFO. If interrupt service latency is long and data is not being unloaded, UARTA
monitors its receive data fill level to match the upper threshold of RTS delay and de-assert RTSA# (6). CTSB# follows
(7) and request UARTB transmitter to suspend data transfer. UARTB stops or finishes sending the data bits in its trans-
mit shift register (8). When receive FIFO data in UARTA is unloaded to match the lower threshold of RTS delay (9),
UARTA re-asserts RTSA# (10), CTSB# recognizes the change (11) and restarts its transmitter and data flow again until
next receive FIFO trigger (12). This same event applies to the reverse direction when UARTA sends data to UARTB
with RTSB# and CTSA# controlling the data flow.
RTSA#
CTSB#
RXA
TXB
Transmitter
Receiver FIFO
Trigger Reached
Auto RTS
Trigger Level
Auto CTS
Monitor
RTSA#
TXB
RXA FIFO
CTSB#
Remote UART
UARTB
Local UART
UARTA
ON
OFF
ON
Suspend
Restart
RTS High
Threshold
Data Starts
ON
OFF
ON
Assert RTS# to Begin
Transmission
1
2
3
4
5
6
7
Receive
Data
RTS Low
Threshold
9
10
11
Receiver FIFO
Trigger Reached
Auto RTS
Trigger Level
Transmitter
Auto CTS
Monitor
RTSB#
CTSA#
RXB
TXA
INTA
(RXA FIFO
Interrupt)
RX FIFO
Trigger Level
RX FIFO
Trigger Level
8
12
RTSCTS1
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| XR16V654 | 制造商:EXAR 制造商全稱:EXAR 功能描述:2.25V TO 3.6V QUAD UART WITH 64-BYTE FIFO |
| XR16V654_0709 | 制造商:EXAR 制造商全稱:EXAR 功能描述:2.25V TO 3.6V QUAD UART WITH 64-BYTE FIFO |
| XR16V654D | 制造商:EXAR 制造商全稱:EXAR 功能描述:2.25V TO 3.6V QUAD UART WITH 64-BYTE FIFO |
| XR16V654DIV | 制造商:Rochester Electronics LLC 功能描述: 制造商:Exar Corporation 功能描述: |
| XR16V654DIV-0A-EB | 功能描述:UART 接口集成電路 Supports V654 64 ld LQFP, ISA Interface RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel |
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