FIGURE 3. PIN OUT ASSIGNMENT FOR 48-PIN QFN PACKAGE AND 80-PIN LQFP PACKAGE
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
1
2
3
4
5
6
7
8
9
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
NC
GND
NC
INTSEL
VC
C
IN
TA
TX
A
NC
TX
B
IN
TB
GN
D
NC
CDB#
RIB#
RXB
VCC
A2
A1
A0
NC
XTAL1
XTAL2
NC
RESET
RXRDY#
TXRDY#
GND
RXC
RIC#
CDC#
NC
VC
C
INT
C
TX
C
NC
TX
D
IN
TD
Intel Mode Only
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
10
11
12
13
14
15
16
17
18
19
20
CDD#
RID#
RXD
VCC
NC
CDA#
RIA#
RXA
GND
D0
D1
D2
NC
D3
D4
D5
D6
D7
XR16 V 564
80- pin LQFP
DS
R
A
#
CT
SA
#
DT
RA
#
RT
S
A
#
CS
A
#
IO
W
#
CSB
#
RT
S
B
#
DT
R
B
#
CT
S
B
#
DS
R
B
#
DS
RD
#
CT
S
D
#
DT
RD
#
RT
S
D
#
CS
D
#
IOR
#
CS
C
#
RT
S
C
#
DT
R
C
#
CT
S
C
#
DS
R
C
#
NC
48
47
46
45
44
43
42
41
40
39
38
37
1
2
3
4
5
6
7
8
9
10
11
12
36
35
34
33
32
31
30
29
28
27
26
25
13
14
15
16
17
18
19
20
21
22
23
24
CTSA#
VCC
RTSA#
INTA
CSA#
TXA
IOW#
TXB
INTB
CSB#
RTSB#
CTSB#
RX
B
16
/6
8#
A2
A1
A0
XT
AL
1
XT
AL
2
R
ESE
T
GN
D
RX
C
CT
S
C
#
VC
C
RXD
CTSD#
GND
RTSD#
INTD
CSD#
TXD
IOR #
TXC
CSC#
INTC
RTSC#
RX
A
GN
D
D7
D6
D5
D4
D3
D2
D1
D0
IN
TS
E
L
VC
C
XR16V564
48-pin QFN
Intel mode
(16/68# pin connected with VCC)
48
47
46
45
44
43
42
41
40
39
38
37
1
2
3
4
5
6
7
8
9
10
11
12
36
35
34
33
32
31
30
29
28
27
26
25
13
14
15
16
17
18
19
20
21
22
23
24
CTSA#
VCC
RTSA#
IRQ#
CS#
TXA
R/W#
TXB
N.C.
A3
RTSB#
CTSB#
RX
B
16
/6
8#
A2
A1
A0
XT
AL
1
XT
AL
2
R
E
SET
#
GN
D
RX
C
CT
S
C
#
VC
C
RXD
CTSD#
GND
RTSD#
N.C.
VCC
TXD
VCC
TXC
A4
N.C.
RTSC#
RX
A
GN
D
D7
D6
D5
D4
D3
D2
D1
D0
GN
D
VC
C
XR16V564
48-pin QFN
Motorola mode
(16/68# pin connected with GND)
XR16V564/564D
3
REV. 1.0.4
2.25V TO 3.6V QUAD UART WITH 32-BYTE FIFO