參數(shù)資料
型號(hào)： XR16V2750IL-0B-EB
廠商： Exar Corporation
文件頁(yè)數(shù)： 31/52頁(yè)
文件大?。?/td> 0K
描述： EVAL BOARD FOR V2750 32QFN
標(biāo)準(zhǔn)包裝： 1
系列： *
XR16V2750
37
REV. 1.0.3
HIGH PERFORMANCE DUART WITH 64-BYTE FIFO
FCTR[5:4]: Transmit/Receive Trigger Table Select
See Table 10 for more details.
FCTR[6]: Scratchpad Swap
Logic 0 = Scratch Pad register is selected as general read and write register. ST16C550 compatible mode.
Logic 1 = FIFO Level Count register (Read-Only), Enhanced Mode Select Register (Write-Only). Number of
characters in transmit or receive FIFO can be read via scratch pad register when this bit is set. Enhanced
Mode Select Register is selected when it is written into.
FCTR[7]: Programmable Trigger Register Select
If using both programmable TX and RX trigger levels, TX trigger levels must be set before RX trigger levels.
Logic 0 = Registers TRG and FC selected for RX.
Logic 1 = Registers TRG and FC selected for TX.
4.19
Enhanced Feature Register (EFR)
Enhanced features are enabled or disabled using this register. Bit 0-3 provide single or dual consecutive
character software flow control selection (see Table 15). When the Xon1 and Xon2 and Xoff1 and Xoff2 modes
are selected, the double 8-bit words are concatenated into two sequential characters. Caution: note that
whenever changing the TX or RX flow control bits, always reset all bits back to logic 0 (disable) before
programming a new setting.
EFR[3:0]: Software Flow Control Select
Single character and dual sequential characters software flow control is supported. Combinations of software
flow control can be selected by programming these bits.
TABLE 14: TRIGGER TABLE SELECT
FCTR
BIT-5
FCTR
BIT-4
TABLE
0
Table-A (TX/RX)
0
1
Table-B (TX/RX)
1
0
Table-C (TX/RX)
1
Table-D (TX/RX)
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