- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄16523 > XR16V2651IL-0B-EB (Exar Corporation)EVAL BOARD FOR V2651 32QFN PDF資料下載
參數(shù)資料
| 型號： | XR16V2651IL-0B-EB |
| 廠商： | Exar Corporation |
| 文件頁數(shù)： | 2/51頁 |
| 文件大?。?/td> | 0K |
| 描述： | EVAL BOARD FOR V2651 32QFN |
| 標準包裝： | 1 |
| 系列： | * |
第1頁當前第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁
XR16V2651
10
HIGH PERFORMANCE DUART WITH 32-BYTE FIFO AND POWERSAVE FEATURE
REV. 1.0.2
2.6
DMA Mode
The device does not support direct memory access. The DMA Mode (a legacy term) in this document doesn’t
mean “direct memory access” but refers to data block transfer operation. The DMA mode affects the state of
the RXRDY# A/B and TXRDY# A/B output pins. The transmit and receive FIFO trigger levels provide additional
flexibility to the user for block mode operation. The LSR bits 5-6 provide an indication when the transmitter is
empty or has an empty location(s) for more data. The user can optionally operate the transmit and receive
FIFO in the DMA mode (FCR bit-3=1). When the transmit and receive FIFO are enabled and the DMA mode is
disabled (FCR bit-3 = 0), the V2651 is placed in single-character mode for data transmit or receive operation.
When DMA mode is enabled (FCR bit-3 = 1), the user takes advantage of block mode operation by loading or
unloading the FIFO in a block sequence determined by the selected trigger level. In this mode, the V2651 sets
the TXRDY# pin when the transmit FIFO becomes full, and sets the RXRDY# pin when the receive FIFO
2.7
INTA and INTB Outputs
The INTA and INTB interrupt output changes according to the operating mode and enhanced features setup.
Table 4 and 5 summarize the operating behavior for the transmitter and receiver. Also see Figures 19
through 24.
TABLE 3: TXRDY# AND RXRDY# OUTPUTS IN FIFO AND DMA MODE
PINS
FCR BIT-0=0
(FIFO DISABLED)
FCR BIT-0=1 (FIFO ENABLED)
FCR Bit-3 = 0
(DMA Mode Disabled)
FCR Bit-3 = 1
(DMA Mode Enabled)
RXRDY# A/B LOW = 1 byte
HIGH = no data
LOW = at least 1 byte in FIFO
HIGH = FIFO empty
HIGH to LOW transition when FIFO reaches the
trigger level, or time-out occurs
LOW to HIGH transition when FIFO empties
TXRDY# A/B LOW = THR empty
HIGH = byte in THR
LOW = FIFO empty
HIGH = at least 1 byte in FIFO
LOW = FIFO has at least 1 empty location
HIGH = FIFO is full
TABLE 4: INTA AND INTB PINS OPERATION FOR TRANSMITTER
FCR BIT-0 = 0
(FIFO DISABLED)
FCR BIT-0 = 1 (FIFO ENABLED)
INTA/B Pin
LOW = a byte in THR
HIGH = THR empty
LOW = FIFO above trigger level
HIGH = FIFO below trigger level or FIFO empty
TABLE 5: INTA AND INTB PIN OPERATION FOR RECEIVER
FCR BIT-0 = 0
(FIFO DISABLED)
FCR BIT-0 = 1
(FIFO ENABLED)
INTA/B Pin
LOW = no data
HIGH = 1 byte
LOW = FIFO below trigger level
HIGH = FIFO above trigger level
相關PDF資料 |
PDF描述 |
|---|---|
| UPJ1C391MPD6TD | CAP ALUM 390UF 16V 20% RADIAL |
| MCP1322T-46LE/OT | IC SUPERVISOR 4.6V OD/PP SOT23-5 |
| EEM28DTMH-S189 | CONN EDGECARD 56POS R/A .156 SLD |
| M3DDA-2436R | IDC CABLE - MKR24A/MC24M/MKR24A |
| VE-JVJ-EZ-S | CONVERTER MOD DC/DC 36V 25W |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| XR16V2651IL32 | 制造商:EXAR 制造商全稱:EXAR 功能描述:HIGH PERFORMANCE DUART WITH 32-BYTE FIFO AND POWERSAVE |
| XR16V2651IL-F | 功能描述:UART 接口集成電路 UART RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel |
| XR16V2651ILTR-F | 制造商:Exar Corporation 功能描述:UART 2-CH 32Byte FIFO 2.5V/3.3V 32-Pin QFN EP T/R 制造商:Exar Corporation 功能描述:XR16V2651ILTR-F |
| XR16V2651IM | 制造商:Rochester Electronics LLC 功能描述: 制造商:Exar Corporation 功能描述: |
| XR16V2651IM-0B-EB | 功能描述:UART 接口集成電路 Supports V2651 48 ld TQFP, PCI Interface RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel |
發(fā)布緊急采購，3分鐘左右您將得到回復。