- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄3766 > XR16V2550IM-F (Exar Corporation)IC UART FIFO 16B 48TQFP PDF資料下載
參數(shù)資料
| 型號(hào)： | XR16V2550IM-F |
| 廠商： | Exar Corporation |
| 文件頁數(shù)： | 25/46頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC UART FIFO 16B 48TQFP |
| 標(biāo)準(zhǔn)包裝： | 250 |
| 特點(diǎn)： | * |
| 通道數(shù)： | 2，DUART |
| FIFO's： | 16 字節(jié) |
| 規(guī)程： | RS232，RS422 |
| 電源電壓： | 2.25 V ~ 3.6 V |
| 帶自動(dòng)流量控制功能： | 是 |
| 帶IrDA 編碼器/解碼器： | 是 |
| 帶故障啟動(dòng)位檢測功能： | 是 |
| 帶調(diào)制解調(diào)器控制功能： | 是 |
| 帶CMOS： | 是 |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 48-TQFP |
| 供應(yīng)商設(shè)備封裝： | 48-TQFP（7x7） |
| 包裝： | 托盤 |
| 其它名稱： | 1016-1464 1016-1464-ND 1016-1648 XR16V2550IM-F-ND |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁當(dāng)前第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁
XR16V2550
31
REV. 1.0.3
HIGH PERFORMANCE DUART WITH 16-BYTE FIFO
LSR[1]: Receiver Overrun Error Flag
Logic 0 = No overrun error (default).
Logic 1 = Overrun error. A data overrun error condition occurred in the receive shift register. This happens
when additional data arrives while the FIFO is full. In this case the previous data in the receive shift register
is overwritten. Note that under this condition the data byte in the receive shift register is not transferred into
the FIFO, therefore the data in the FIFO is not corrupted by the error.
LSR[2]: Receive Data Parity Error Tag
Logic 0 = No parity error (default).
Logic 1 = Parity error. The receive character in RHR does not have correct parity information and is suspect.
This error is associated with the character available for reading in RHR.
LSR[3]: Receive Data Framing Error Tag
Logic 0 = No framing error (default).
Logic 1 = Framing error. The receive character did not have a valid stop bit(s). This error is associated with
the character available for reading in RHR.
LSR[4]: Receive Break Error Tag
Logic 0 = No break condition (default).
Logic 1 = The receiver received a break signal (RX was LOW for at least one character frame time). In the
FIFO mode, only one break character is loaded into the FIFO.
LSR[5]: Transmit Holding Register Empty Flag
This bit is the Transmit Holding Register Empty indicator. The THR bit is set to a logic 1 when the last data byte
is transferred from the transmit holding register to the transmit shift register. The bit is reset to logic 0
concurrently with the data loading to the transmit holding register by the host. In the FIFO mode this bit is set
when the transmit FIFO is empty, it is cleared when the transmit FIFO contains at least 1 byte.
LSR[6]: THR and TSR Empty Flag
This bit is set to a logic 1 whenever the transmitter goes idle. It is set to logic 0 whenever either the THR or
TSR contains a data character. In the FIFO mode this bit is set to a logic 1 whenever the transmit FIFO and
transmit shift register are both empty.
LSR[7]: Receive FIFO Data Error Flag
Logic 0 = No FIFO error (default).
Logic 1 = A global indicator for the sum of all error bits in the RX FIFO. At least one parity error, framing error
or break indication is in the FIFO data. This bit clears when there is no more error(s) in any of the bytes in the
RX FIFO.
4.9
Modem Status Register (MSR) - Read Only
This register provides the current state of the modem interface input signals. Lower four bits of this register are
used to indicate the changed information. These bits are set to a logic 1 whenever a signal from the modem
changes state. These bits may be used for general purpose inputs when they are not used with modem
signals.
MSR[0]: Delta CTS# Input Flag
Logic 0 = No change on CTS# input (default).
Logic 1 = The CTS# input has changed state since the last time it was monitored. A modem status interrupt
will be generated if MSR interrupt is enabled (IER bit-3).
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MAX7311AWG+T | IC I/O EXPANDER I2C 16B 24SOIC |
| XR16L2750CM-F | IC UART FIFO 64B DUAL 48TQFP |
| XR20M1172IL32-F | IC UART FIFO I2C/SPI 64B 32QFN |
| XR88C192CV-F | IC UART FIFO DUAL 44LQFP |
| XR16L2550IM-F | IC UART FIFO 16B DUAL 48TQFP |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| XR16V2550IMTR-F | 制造商:Exar Corporation 功能描述:UART 2-CH 16Byte FIFO 2.5V/3.3V 48-Pin TQFP T/R 制造商:Exar Corporation 功能描述:XR16V2550IMTR-F |
| XR16V2551 | 制造商:EXAR 制造商全稱:EXAR 功能描述:HIGH PERFORMANCE DUART WITH 16-BYTE FIFO AND POWERSAVE FEATURE |
| XR16V2551_07 | 制造商:EXAR 制造商全稱:EXAR 功能描述:HIGH PERFORMANCE DUART WITH 16-BYTE FIFO AND POWERSAVE FEATURE |
| XR16V2551IL | 制造商:Rochester Electronics LLC 功能描述: 制造商:Exar Corporation 功能描述: |
| XR16V2551IL-0B-EB | 功能描述:UART 接口集成電路 Supports V2551 32pin QFN, PCI Interface RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。