REV. 1.0.3 HIGH PERFORMANCE DUART WITH 16-BYTE FIFO 2.13 Auto RTS (Hardware) Flow Control Automatic RTS hardware flo" />
參數(shù)資料
型號： XR16V2550ILTR-F
廠商： Exar Corporation
文件頁數(shù)： 7/46頁
文件大小： 0K
描述： IC UART FIFO 16B DUAL 32QFN
標準包裝： 3,000
特點： *
通道數(shù)： 2，DUART
FIFO's： 16 字節(jié)
規(guī)程： RS232，RS422
電源電壓： 2.25 V ~ 3.6 V
帶自動流量控制功能： 是
帶IrDA 編碼器/解碼器： 是
帶故障啟動位檢測功能： 是
帶調制解調器控制功能： 是
帶CMOS： 是
安裝類型： 表面貼裝
封裝/外殼： 32-VFQFN 裸露焊盤
供應商設備封裝： 32-QFN 裸露焊盤（5x5）
包裝： 帶卷 (TR)
XR16V2550
15
REV. 1.0.3
HIGH PERFORMANCE DUART WITH 16-BYTE FIFO
2.13
Auto RTS (Hardware) Flow Control
Automatic RTS hardware flow control is used to prevent data overrun to the local receiver FIFO. The RTS#
output is used to request remote unit to suspend/resume data transmission. The auto RTS flow control
features is enabled to fit specific application requirement (see Figure 10):
Enable auto RTS flow control using EFR bit-6.
The auto RTS function must be started by asserting RTS# output pin (MCR bit-1 to logic 1 after it is enabled).
If using the Auto RTS interrupt:
Enable RTS interrupt through IER bit-6 (after setting EFR bit-4). The UART issues an interrupt when the
RTS# pin makes a transition from low to high: ISR bit-5 will be set to logic 1.
2.14
Auto RTS Hysteresis
The V2550 has a new feature that provides flow control trigger hysteresis while maintaining compatibility with
the XR16C850, ST16C650A and ST16C550 family of UARTs. With the Auto RTS function enabled, an interrupt
is generated when the receive FIFO reaches the selected RX trigger level. The RTS# pin will not be forced
HIGH (RTS off) until the receive FIFO reaches one trigger level above the selected trigger level in the trigger
table (Table 11). The RTS# pin will return LOW after the RX FIFO is unloaded to one level below the selected
trigger level. Under the above described conditions, the V2550 will continue to accept data until the receive
FIFO gets full. The Auto RTS function is initiated when the RTS# output pin is asserted LOW (RTS On).
TABLE 6: AUTO RTS (HARDWARE) FLOW CONTROL
RX TRIGGER LEVEL
INT PIN ACTIVATION
RTS# DE-ASSERTED (HIGH)
(CHARACTERS IN RX FIFO)
RTS# ASSERTED (LOW)
(CHARACTERS IN RX FIFO)
1
4
0
4
8
1
8
14
4
14
8
2.15
Auto CTS Flow Control
Automatic CTS flow control is used to prevent data overrun to the remote receiver FIFO. The CTS# input is
monitored to suspend/restart the local transmitter. The auto CTS flow control feature is selected to fit specific
application requirement (see Figure 10):
Enable auto CTS flow control using EFR bit-7.
If using the Auto CTS interrupt:
Enable CTS interrupt through IER bit-7 (after setting EFR bit-4). The UART issues an interrupt when the
CTS# pin is de-asserted (HIGH): ISR bit-5 will be set to 1, and UART will suspend transmission as soon as
the stop bit of the character in process is shifted out. Transmission is resumed after the CTS# input is re-
asserted (LOW), indicating more data may be sent.
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相關代理商/技術參數(shù)
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