REV. 1.1.1 HIGH PERFORMANCE DUART WITH 64-BYTE FIFO DLD[6]: Auto RS-485 Direction Control
參數(shù)資料
型號(hào)： XR16M752IM48-F
廠商： Exar Corporation
文件頁(yè)數(shù)： 31/54頁(yè)
文件大?。?/td> 0K
描述： IC UART FIFO 34B DUAL 48TQFP
標(biāo)準(zhǔn)包裝： 250
特點(diǎn)： *
通道數(shù)： 2，DUART
FIFO's： 64 字節(jié)
規(guī)程： RS232，RS422，RS485
電源電壓： 1.62 V ~ 3.63 V
帶自動(dòng)流量控制功能： 是
帶IrDA 編碼器/解碼器： 是
帶故障啟動(dòng)位檢測(cè)功能： 是
帶調(diào)制解調(diào)器控制功能： 是
帶CMOS： 是
安裝類(lèi)型： 表面貼裝
封裝/外殼： 48-TQFP
供應(yīng)商設(shè)備封裝： 48-TQFP（7x7）
包裝： 托盤(pán)
其它名稱： 1016-1461
1016-1461-ND
1016-1649
XR16M752IM48-F-ND
XR16M752/XR68M752
37
REV. 1.1.1
HIGH PERFORMANCE DUART WITH 64-BYTE FIFO
DLD[6]: Auto RS-485 Direction Control
Logic 0 = Standard ST16C550 mode. Transmitter generates an interrupt when transmit holding register
becomes empty and transmit shift register is shifting data out. The RTS# output can be used as a general
purpose output or for Auto RTS flow control.
Logic 1 = Enable Auto RS485 Direction Control function. The direction control signal, RTS# pin, changes its
output logic state from HIGH to LOW one bit time after the last stop bit of the last character is shifted out.
Also, the Transmit interrupt generation is delayed until the transmitter shift register becomes empty. The
RTS# output pin will automatically return to a HIGH when a data byte is loaded into the TX FIFO. See
DLD[7]: Infrared Encoder/Decoder Enable
Logic 0 = Enable the standard modem receive and transmit input/output interface (default).
Logic 1 = Enable infrared IrDA receive and transmit inputs/outputs. The TX/RX output/input are routed to the
infrared encoder/decoder. The data input and output levels conform to the IrDA infrared interface
requirement. While in this mode, the infrared TX output will be idling LOW. SEE ”INFRARED MODE” ON
4.14
Enhanced Feature Register (EFR)
Enhanced features are enabled or disabled using this register. Bit 0-3 provide single or dual consecutive
character software flow control selection (see Table 15). When the Xon1 and Xon2 and Xoff1 and Xoff2 modes
are selected, the double 8-bit words are concatenated into two sequential characters. Caution: note that
whenever changing the TX or RX flow control bits, always reset all bits back to logic 0 (disable) before
programming a new setting.
EFR[3:0]: Software Flow Control Select
Single character and dual sequential characters software flow control is supported. Combinations of software
flow control can be selected by programming these bits.
0
1
8X
1
X
4X
TABLE 15: SOFTWARE FLOW CONTROL FUNCTIONS
EFR BIT-3
CONT-3
EFR BIT-2
CONT-2
EFR BIT-1
CONT-1
EFR BIT-0
CONT-0
TRANSMIT AND RECEIVE SOFTWARE FLOW CONTROL
0
No TX and RX flow control (default and reset)
0
X
No transmit flow control
1
0
X
Transmit Xon1, Xoff1
0
1
X
Transmit Xon2, Xoff2
1
X
Transmit Xon1 and Xon2, Xoff1 and Xoff2
X
0
No receive flow control
X
1
0
Receiver compares Xon1, Xoff1
X
0
1
Receiver compares Xon2, Xoff2
1
0
1
Transmit Xon1, Xoff1
Receiver compares Xon1 and Xon2, Xoff1 and Xoff2
TABLE 14: SAMPLING RATE SELECT
DLD[5]
DLD[4]
SAMPLING RATE
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