XR16M680
17
REV. 1.0.0
1.62V TO 3.63V HIGH PERFORMANCE UART WITH 32-BYTE FIFO
FIGURE 11. RECEIVER OPERATION IN NON-FIFO MODE
FIGURE 12. RECEIVER OPERATION IN FIFO AND AUTO RTS FLOW CONTROL MODE
Receive Data Shift
Register (RSR)
Receive
Data Byte
and Errors
RHR Interrupt (ISR bit-2)
Receive Data
Holding Register
(RHR)
RXFIFO1
16X or 8X or 4X Clock
( DLD[5:4] )
Receive Data Characters
Data Bit
Validation
Error
Tags in
LSR bits
4:2
Rece ive Da ta S hift
R egister (R S R )
R X FIFO 1
16X or 8X o r 4X C lock
( DLD[5:4] )
Err
o
rT
a
g
s
(32
-s
e
ts)
Er
ro
rT
a
g
s
i
n
LS
R
b
its
4:
2
R ece ive D ata C haracte rs
D a ta B it
V alidation
Receive
D ata FIF O
Receive
Data
Rece ive Da ta
B yte and E rrors
R H R Interrupt (IS R bit-2 ) prog ram m ed for
de sired FIFO trigger level.
FIFO is E nab led by F C R b it-0=1
R TS # de -asserts w hen data fills abo ve the flo w
con trol trig ger le vel to su spend rem o te tran sm itter.
E na ble by E FR b it-6=1, M C R bit-1.
R TS# re-asserts w he n data falls be low the flow
contro l trigge r level to resta rt rem o te tran sm itter.
E na ble by E FR b it-6=1, M C R bit-1.
32 bytes by 11-bit w ide
FIFO
Trigger=16
D ata falls to
8
D ata fills to
24
E xam ple
: - R X FIFO trigger level selected at 16 bytes
(See N ote Below )