參數(shù)資料
型號(hào)： XR16M654IV-0B-EVB
廠商： Exar Corporation
文件頁(yè)數(shù)： 57/58頁(yè)
文件大小： 0K
描述： EVAL BOARD FOR XR16M654-B 64LQFP
標(biāo)準(zhǔn)包裝： 1
系列： *
XR16M654/654D
8
1.62V TO 3.63V QUAD UART WITH 64-BYTE FIFO
REV. 1.0.0
FSRS#
-
76
I
FIFO Status Register Select (active low
input with internal pull-up).
The content of the FSTAT register is placed
on the data bus when this pin becomes
active. However it should be noted, D0-D3
contain the inverted logic states of TXRDY#
A-D pins, and D4-D7 the logic states (un-
inverted) of RXRDY# A-D pins. A valid
address is not required when reading this
status register.
MODEM OR SERIAL I/O INTERFACE
TXA
TXB
TXC
TXD
6
8
28
30
8
10
39
41
17
19
51
53
10
12
50
52
14
16
65
67
O
UART channels A-D Transmit Data and
infrared transmit data. Standard transmit
and receive interface is enabled when
MCR[6] = 0. In this mode, the TX signal will
be a logic 1 during reset, or idle (no data).
Infrared IrDA transmit and receive interface
is enabled when MCR[6] = 1. In the Infra-
red mode, the inactive state (no data) for
the Infrared encoder/decoder interface is a
logic 0.
IRTXA
IRTXB
IRTXC
IRTXD
-
6
24
57
75
O
UART channel A-D Infrared Transmit Data.
The inactive state (no data) for the Infrared
encoder/decoder interface is LOW.
Regardless of the logic state of MCR bit-6,
this pin will be operating in the Infrared
mode.
RXA
RXB
RXC
RXD
48
13
22
36
62
20
29
51
7
29
41
63
77
25
37
65
97
34
47
85
I
UART channel A-D Receive Data or infra-
red receive data. Normal receive data input
must idle HIGH.
RTSA#
RTSB#
RTSC#
RTSD#
3
11
25
33
5
13
36
44
14
22
48
56
7
15
47
55
11
19
62
70
O
UART channels A-D Request-to-Send
(active low) or general purpose output. This
output must be asserted prior to using auto
RTS flow control, see EFR[6], MCR[1], and
IER[6]. Also see
Figure 12. If these out-
puts are not used, leave them unconnected.
CTSA#
CTSB#
CTSC#
CTSD#
1
12
23
35
2
16
33
47
11
25
45
59
4
18
44
58
8
22
59
73
I
UART channels A-D Clear-to-Send (active
low) or general purpose input. It can be
used for auto CTS flow control, see EFR[7],
and IER[7]. Also see
inputs should be connected to VCC when
not used.
DTRA#
DTRB#
DTRC#
DTRD#
-
3
15
34
46
12
24
46
58
5
17
45
57
9
21
60
72
O
UART channels A-D Data-Terminal-Ready
(active low) or general purpose output. If
these outputs are not used, leave them
unconnected.
Pin Description
NAME
48-QFN
PIN #
64-LQFP
PIN #
68-PLCC
PIN#
80-LQFP
PIN #
100-QFP
PIN #
TYPE
DESCRIPTION
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