REV. 1.0.1 1.62V TO 3.63V UART WITH 16-BYTE FIFO AND VLIO INTERFACE PIN DESCRIPTIONS Pin Description N
參數(shù)資料
型號(hào)： XR16M581IL32-F
廠商： Exar Corporation
文件頁(yè)數(shù)： 23/51頁(yè)
文件大小： 0K
描述： IC UART FIFO 16B 32QFN
標(biāo)準(zhǔn)包裝： 490
特點(diǎn)： *
通道數(shù)： 1，UART
FIFO's： 16 字節(jié)
規(guī)程： RS232，RS422，RS485
電源電壓： 1.62 V ~ 3.63 V
帶自動(dòng)流量控制功能： 是
帶IrDA 編碼器/解碼器： 是
帶故障啟動(dòng)位檢測(cè)功能： 是
帶調(diào)制解調(diào)器控制功能： 是
帶CMOS： 是
安裝類型： 表面貼裝
封裝/外殼： 32-VFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝： 32-QFN 裸露焊盤（5x5）
包裝： 托盤
其它名稱： 1016-1457
XR16M581IL32-F-ND
XR16M581
3
REV. 1.0.1
1.62V TO 3.63V UART WITH 16-BYTE FIFO AND VLIO INTERFACE
PIN DESCRIPTIONS
Pin Description
NAME
24-QFN
PIN#
32-QFN
PIN#
25-BGA
PIN#
TYPE
DESCRIPTION
DATA BUS INTERFACE
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
20
21
22
23
24
1
2
3
29
30
31
32
1
3
4
5
C1
D2
E2
D1
E1
B2
E3
C2
I/O
Multiplexed Address/Data lines [7:0]. The register address is
latched on the rising edge of the LLA#. After the LLA# signal goes
high, the UART enters the data phase where the data is placed on
these lines.
IOR#
12
14
A5
I
Read strobe (active low). The falling edge instigates an internal
read cycle and retrieves the data byte from an internal register
pointed by the latched address. The UART places the data byte on
the data bus to allow the host processor to read it on the rising
edge.
IOW#
10
12
E5
I
Write strobe (active low). The falling edge instigates the internal
write cycle and the rising edge transfers the data byte on the data
bus to an internal register pointed by the latched address.
CS#
6
8
D3
I
Chip select (active low). The falling edge starts the access to the
UART. A read or write is determined by the IOR# and IOW# sig-
nals.
LLA#
14
19
A4
I
Latch Lower Address (active low). The register address is latched
on the rising edge of the LLA# signal. After the LLA# goes high, the
device enters the data phase where the data is placed on the
AD[7:0] lines.
INT
15
20
B4
O
Interrupt output (active high). The output state is defined by the
user through the software setting of MCR[3]. INT is set to the active
mode when MCR[3] is set to a logic 1. INT is set to the three state
mode when MCR[3] is set to a logic 0. See MCR[3].
MODEM OR SERIAL I/O INTERFACE
TX
5
7
E4
O
UART Transmit Data or infrared encoder data. Standard transmit
and receive interface is enabled when MCR[6] = 0. In this mode,
the TX signal will be a logic 1 during reset or idle (no data). Infrared
IrDA transmit and receive interface is enabled when MCR[6] = 1. In
the Infrared mode, the inactive state (no data) for the Infrared
encoder/decoder interface is a logic 0. If it is not used, leave it
unconnected.
RX
4
6
C3
I
UART Receive Data or infrared receive data. Normal receive data
input must idle at logic 1 condition. The infrared receiver idles at
logic 0. This input should be connected to VCC when not used.
RTS#
16
21
A3
O
UART Request-to-Send (active low) or general purpose output.
This output must be asserted prior to using auto RTS flow control,
see EFR[6], MCR[1] and IER[6]. This pin can also be used as the
Auto RS-485 Half-duplex Direction control output, see FCTR[3] and
EMSR[3].
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