參數(shù)資料
型號： XR16M580IB25TR-F
廠商： Exar Corporation
文件頁數(shù)： 13/56頁
文件大小： 0K
描述： IC UART FIFO 16B 25BGA
標(biāo)準(zhǔn)包裝： 2,500
特點(diǎn)： *
通道數(shù)： 1，UART
FIFO's： 16 字節(jié)
規(guī)程： RS232，RS422，RS485
電源電壓： 1.62 V ~ 3.63 V
帶自動流量控制功能： 是
帶IrDA 編碼器/解碼器： 是
帶故障啟動位檢測功能： 是
帶調(diào)制解調(diào)器控制功能： 是
帶CMOS： 是
安裝類型： 表面貼裝
封裝/外殼： 25-WFBGA
供應(yīng)商設(shè)備封裝： 25-BGA（3x3）
包裝： 帶卷 (TR)
XR16M580
20
1.62V TO 3.63V HIGH PERFORMANCE UART WITH 16-BYTE FIFO
REV. 1.0.0
interrupt and place the address byte in the RX FIFO. The software then examines the byte and enables the
receiver if the address matches its slave address, otherwise, it does not enable the receiver.
If the receiver has been enabled, the receiver will receive the subsequent data. If an address byte is received,
it will generate an LSR interrupt. The software again examines the byte and if the address matches its slave
address, it does not have to do anything. If the address does not match its slave address, then the receiver
should be disabled.
2.15.1
Auto Address Detection
Auto address detection mode is enabled when MSR[6] = 1 (requires EFR[4] = 1) and EFR bit-5 = 1. The
desired slave address will need to be written into the XOFF2 register. The receiver will try to detect an address
byte that matches the porgrammed character in the XOFF2 register. If the received byte is a data byte or an
address byte that does not match the programmed character in the XOFF2 register, the receiver will discard
these data.
Upon receiving an address byte that matches the XOFF2 character, the receiver will be
automatically enabled if not already enabled, and the address character is pushed into the RX FIFO along with
the parity bit (in place of the parity error bit). The receiver also generates an LSR interrupt. The receiver will
then receive the subsequent data. If another address byte is received and this address does not match the
programmed XOFF2 character, then the receiver will automatically be disabled and the address byte is
ignored. If the address byte matches XOFF2, the receiver will put this byte in the RX FIFO along with the parity
bit in the parity error bit.
2.16
Infrared Mode
The M580 UART includes the infrared encoder and decoder compatible to the IrDA (Infrared Data Association)
version 1.0 and 1.1. The IrDA 1.0 standard that stipulates the infrared encoder sends out a 3/16 of a bit wide
HIGH-pulse for each “0” bit in the transmit data stream with a data rate up to 115.2 Kbps. For the IrDA 1.1
standard, the infrared encoder sends out a 1/4 of a bit time wide HIGH-pulse for each "0" bit in the transmit
data stream with a data rate up to 1.152 Mbps. This signal encoding reduces the on-time of the infrared LED,
hence reduces the power consumption. See Figure 14 below.
The infrared encoder and decoder are enabled by setting MCR register bit-6 to a ‘1’. With this bit enabled, the
infrared encoder and decoder is compatible to the IrDA 1.0 standard. For the infrared encoder and decoder to
be compatible to the IrDA 1.1 standard, MSR bit-7 will also need to be set to a ’1’ when EFR bit-4 is set to ’1’.
Likewise, the RX input assumes an idle level of logic zero from a reset and power up, see Figure 14.
Typically, the wireless infrared decoder receives the input pulse from the infrared sensing diode on the RX pin.
Each time it senses a light pulse, it returns a logic 1 to the data bit stream.
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