Exar Corporation 48720 Kato Road, Fremont CA, 94538 (510) 668-7000 FAX (510) 668-7017 www.exar.com
XR16M564/564D
1.62V TO 3.63V QUAD UART WITH 32-BYTE FIFO
MAY 2008
REV. 1.0.0
GENERAL DESCRIPTION
The XR16M5641 (M564) is an enhanced quad
Universal Asynchronous Receiver and Transmitter
(UART) with 32 bytes of transmit and receive FIFOs,
programmable transmit and receive FIFO trigger
levels, automatic hardware and software flow control,
and data rates of up to 16 Mbps at 4X sampling rate.
Each UART has a set of registers that provide the
user with operating status and control, receiver error
indications, and modem serial interface controls. An
internal
loopback
capability
allows
onboard
diagnostics. The M564 is available in a 48-pin QFN,
64-pin
LQFP,
68-pin
PLCC
and
80-pin
LQFP
packages. The 64-pin and 80-pin packages only offer
the 16 mode interface, but the 48 and 68 pin
packages offer an additional 68 mode interface which
allows easy integration with Motorola processors.
The XR16M564IV (64-pin) offers three state interrupt
output while the XR16M564DIV provides continuous
interrupt output. The XR16M564 is compatible with
the industry standard ST16C554 and ST16C654/
654D.
NOTE: 1 Covered by U.S. Patent #5,649,122.
FEATURES
Pin-to-pin compatible with ST16C454, ST16C554,
TI’s TL16C754B and NXP’s SC16C754B
Intel or Motorola Data Bus Interface select
Four independent UART channels
■ Register Set Compatible to 16C550
■ Data rates of up to 16 Mbps
■ 32 byte Transmit FIFO
■ 32 byte Receive FIFO with error tags
■ 4 Selectable TX and RX FIFO Trigger Levels
■ Automatic Hardware (RTS/CTS) Flow Control
■ Automatic Software (Xon/Xoff) Flow Control
■ Programmable Xon/Xoff characters
■ Wireless Infrared (IrDA 1.0) Encoder/Decoder
■ Full modem interface
1.62V to 3.63V supply operation
Sleep Mode with automatic wake-up
Crystal oscillator or external clock input
APPLICATIONS
Portable Appliances
Telecommunication Network Routers
Ethernet Network Routers
Cellular Data Devices
Factory Automation and Process Controls
FIGURE 1. XR16M564 BLOCK DIAGRAM
XTAL1
XTAL2
Crystal Osc/Buffer
Data Bus
Interface
UART Channel A
32 Byte TX FIFO
32 Byte RX FIFO
BRG
IR
ENDEC
TX & RX
UART
Regs
1.62V to 3.6V VCC
GND
564 B LK
TXB, RXB, DTRB#,
DSRB #, RTSB#, CTSB#,
CDB#, RIB#
UART Channel B
(same as Channel A)
A2:A0
D7:D0
CSA#
16/68#
CSB#
INTA
INTB
IOW#
IOR#
Reset
INTSEL
TXRDY# A-D
RXRDY # A-D
UART Channel C
(same as Channel A)
TXA, RXA, DTRA#,
DSRA #, RTSA#, CTSA#,
CDA#, RIA#
TXC, RXC, DTRC#,
DSRC#, RTSC#, CTSC#,
CDC#, RIC#
UART Channel D
(same as Channel A)
TXD, RXD, DTRD#,
DSRD#, RTSD#, CTSD#,
CDD#, RID#
CSC#
CSD#
INTC
INTD
CLKSEL