XR16M554/554D
17
REV. 1.0.0
1.62V TO 3.63V QUAD UART WITH 16-BYTE FIFO
FIGURE 10. RECEIVER OPERATION IN FIFO
Rece ive Da ta S hift
R egister (R S R )
R X FIFO 1
16X C lock
E
rro
rTags
(1
6
-s
e
ts
)
Er
ro
rT
a
g
s
in
LS
R
bit
s
4:
2
R ece ive D ata C haracte rs
D a ta B it
V alidation
Receive
D ata FIF O
Receive
Data
Rece ive Da ta
B yte and E rrors
R H R Interrupt (IS R bit-2 ) prog ram m ed for
de sired FIFO trigger level.
FIFO is E nab led by F C R b it-0=1
A sking fo r stop ping d ata w h en da ta fills ab ove th e flow
con trol trig ger le vel to su spend rem o te tran sm itter.
A sking for sendin g data w hen data falls below the flow
con trol trig ger le vel to restart rem ote transm itter.
16 bytes by 11-bit w ide
FIFO
T rigger=8
D ata falls to
4
D ata fills to
14
E xam ple
: - R X F IF O trigger level selected at 8 bytes
(See N ote Below )