REV. 1.0.2 HIGH PERFORMANCE DUART WITH 32-BYTE FIFO AND POWERSAVE FEATURE 2.3 Device Identification and Revision The " />
參數(shù)資料
型號(hào)： XR16M2651IL32-F
廠商： Exar Corporation
文件頁(yè)數(shù)： 51/51頁(yè)
文件大小： 0K
描述： IC UART FIFO 32B DUAL 32QFN
標(biāo)準(zhǔn)包裝： 490
特點(diǎn)： *
通道數(shù)： 2，DUART
FIFO's： 32 字節(jié)
規(guī)程： RS232，RS422
電源電壓： 1.62 V ~ 3.63 V
帶自動(dòng)流量控制功能： 是
帶IrDA 編碼器/解碼器： 是
帶故障啟動(dòng)位檢測(cè)功能： 是
帶調(diào)制解調(diào)器控制功能： 是
帶CMOS： 是
安裝類(lèi)型： 表面貼裝
封裝/外殼： 32-VFQFN 裸露焊盤(pán)
供應(yīng)商設(shè)備封裝： 32-QFN 裸露焊盤(pán)（5x5）
包裝： 托盤(pán)
XR16M2651
9
REV. 1.0.2
HIGH PERFORMANCE DUART WITH 32-BYTE FIFO AND POWERSAVE FEATURE
2.3
Device Identification and Revision
The XR16M2651 provides a Device Identification code and a Device Revision code to distinguish the part from
other devices and revisions. To read the identification code from the part, it is required to set the baud rate
generator registers DLL and DLM both to 0x00 (DLD = 0xXX). Now reading the content of the DVID will
provide 0x06 for the XR16M2651 and reading the content of DREV will provide the revision of the part; for
example, a reading of 0x01 means revision A.
2.4
Channel A and B Selection
The UART provides the user with the capability to bi-directionally transfer information between an external
CPU and an external serial communication device. During Intel Bus Mode (16/68# pin connected to VCC), a
logic 0 on chip select pins, CSA# or CSB#, allows the user to select UART channel A or B to configure, send
transmit data and/or unload receive data to/from the UART. Selecting both UARTs can be useful during power
up initialization to write to the same internal registers, but do not attempt to read from both UARTs
simultaneously. Individual channel select functions are shown in Table 1.
During Motorola Bus Mode (16/68# pin connected to GND), the package interface pins are configured for
connection with Motorola, and other popular microprocessor bus types. In this mode the M2651 decodes an
additional address, A3, to select one of the UART ports. The A3 address decode function is used only when in
the Motorola Bus Mode. See Table 2.
Each UART channel in the M2651 has a set of enhanced registers for control, monitoring and data loading and
unloading. The configuration register set is compatible to those already available in the standard single
16C550 and dual ST16C2550. These registers function as data holding registers (THR/RHR), interrupt status
and control registers (ISR/IER), a FIFO control register (FCR), receive line status and control registers (LSR/
LCR), modem status and control registers (MSR/MCR), programmable data rate (clock) divisor registers (DLL/
DLM/DLD), and a user accessible Scratchpad Register (SPR).
Beyond the general 16C2550 features and capabilities, the M2651 offers enhanced feature registers (EFR,
Xon/Xoff 1, Xon/Xoff 2) that provide automatic RTS and CTS hardware flow control, and Xon/Xoff software flow
control. All the register functions are discussed in full detail later in “Section 3.0, UART INTERNAL
TABLE 1: CHANNEL A AND B SELECT IN 16 MODE
CSA#
CSB#
FUNCTION
1
UART de-selected
0
1
Channel A selected
1
0
Channel B selected
0
Channel A and B selected
TABLE 2: CHANNEL A AND B SELECT IN 68 MODE
CS#
A3
FUNCTION
1
N/A
UART de-selected
0
Channel A selected
0
1
Channel B selected
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