參數(shù)資料
型號(hào)： XR16L2750CJ
廠商： EXAR CORP
元件分類： 微控制器/微處理器
英文描述： 2.25V TO 5.5V DUART WITH 64-BYTE FIFO
中文描述： 2 CHANNEL(S), 6.25M bps, SERIAL COMM CONTROLLER, PQCC44
封裝： PLASTIC, LCC-44
文件頁(yè)數(shù)： 48/49頁(yè)
文件大?。?/td> 602K
代理商： XR16L2750CJ
á
XR16L2750
2.25V TO 5.5V DUART WITH 64-BYTE FIFO
REV. 1.0.0
I
TABLE OF CONTENTS
GENERAL DESCRIPTION.................................................................................................1
A
PPLICATIONS
.............................................................................................................................................1
F
EATURES
..................................................................................................................................................1
F
IGURE
1. XR16L2750 B
LOCK
D
IAGRAM
................................................................................................................................................. 1
F
IGURE
2. P
IN
O
UT
A
SSIGNMENT
............................................................................................................................................................. 2
ORDERING
INFORMATION
.............................................................................................................................2
PIN DESCRIPTIONS .........................................................................................................3
1.0 Product DESCRIPTION ........................................................................................................... 6
2.0 FUNCTIONAL DESCRIPTIONS ............................................................................................... 7
2.1 CPU I
NTERFACE
................................................................................................................................. 7
2.2 5-V
OLT
T
OLERANT
I
NPUTS
.................................................................................................................. 7
2.3 D
EVICE
R
ESET
.................................................................................................................................... 7
2.4 D
EVICE
I
DENTIFICATION
AND
R
EVISION
................................................................................................ 7
2.5 C
HANNEL
A
AND
B S
ELECTION
............................................................................................................ 7
F
IGURE
3. XR16L2750 D
ATA
B
US
I
NTERCONNECTIONS
........................................................................................................................... 7
2.6 C
HANNEL
A
AND
B I
NTERNAL
R
EGISTERS
............................................................................................ 8
2.7 DMA M
ODE
........................................................................................................................................ 8
T
ABLE
1: C
HANNEL
A
AND
B S
ELECT
....................................................................................................................................................... 8
T
ABLE
2: TXRDY#
AND
RXRDY# O
UTPUTS
IN
FIFO
AND
DMA M
ODE
.................................................................................................... 8
2.8 INTA
AND
INTB O
UTPUTS
.................................................................................................................. 9
2.9 C
RYSTAL
O
SCILLATOR
OR
E
XTERNAL
C
LOCK
I
NPUT
............................................................................. 9
T
ABLE
3: INTA
AND
INTB P
INS
O
PERATION
FOR
T
RANSMITTER
................................................................................................................ 9
T
ABLE
4: INTA
AND
INTB P
IN
O
PERATION
F
OR
R
ECEIVER
....................................................................................................................... 9
F
IGURE
4. T
YPICAL
OSCILLATOR
CONNECTIONS
........................................................................................................................................ 9
2.10 P
ROGRAMMABLE
B
AUD
R
ATE
G
ENERATOR
....................................................................................... 10
F
IGURE
5. E
XTERNAL
C
LOCK
C
ONNECTION
FOR
E
XTENDED
D
ATA
R
ATE
................................................................................................. 10
F
IGURE
6. B
AUD
R
ATE
G
ENERATOR
AND
P
RESCALER
............................................................................................................................ 10
2.11 T
RANSMITTER
................................................................................................................................. 11
2.11.1 Transmit Holding Register (THR) - Write Only....................................................................................... 11
2.11.2 Transmitter Operation in non-FIFO Mode.............................................................................................. 11
T
ABLE
5: T
YPICAL
DATA
RATES
WITH
A
14.7456 MH
Z
CRYSTAL
OR
EXTERNAL
CLOCK
.............................................................................. 11
2.11.3 Transmitter Operation in FIFO Mode ..................................................................................................... 12
2.12 R
ECEIVER
....................................................................................................................................... 12
F
IGURE
7. T
RANSMITTER
O
PERATION
IN
NON
-FIFO M
ODE
...................................................................................................................... 12
F
IGURE
8. T
RANSMITTER
O
PERATION
IN
FIFO
AND
F
LOW
C
ONTROL
M
ODE
............................................................................................. 12
2.12.1 Receive Holding Register (RHR) - Read-Only....................................................................................... 13
F
IGURE
9. R
ECEIVER
O
PERATION
IN
NON
-FIFO M
ODE
........................................................................................................................... 13
F
IGURE
10. R
ECEIVER
O
PERATION
IN
FIFO
AND
A
UTO
RTS F
LOW
C
ONTROL
M
ODE
............................................................................... 13
2.13 A
UTO
RTS (H
ARDWARE
) F
LOW
C
ONTROL
....................................................................................... 14
2.14 A
UTO
RTS H
YSTERESIS
................................................................................................................. 14
2.15 A
UTO
CTS F
LOW
C
ONTROL
........................................................................................................... 14
F
IGURE
11. A
UTO
RTS
AND
CTS F
LOW
C
ONTROL
O
PERATION
.............................................................................................................. 15
2.16 A
UTO
X
ON
/X
OFF
(S
OFTWARE
) F
LOW
C
ONTROL
............................................................................... 16
2.17 S
PECIAL
C
HARACTER
D
ETECT
........................................................................................................ 16
2.18 A
UTO
RS485 H
ALF
-
DUPLEX
C
ONTROL
........................................................................................... 16
T
ABLE
6: A
UTO
X
ON
/X
OFF
(S
OFTWARE
) F
LOW
C
ONTROL
....................................................................................................................... 16
2.19 I
NFRARED
M
ODE
............................................................................................................................. 17
2.20 S
LEEP
M
ODE
WITH
A
UTO
W
AKE
-U
P
............................................................................................... 17
F
IGURE
12. I
NFRARED
T
RANSMIT
D
ATA
E
NCODING
AND
R
ECEIVE
D
ATA
D
ECODING
................................................................................. 17
2.21 I
NTERNAL
L
OOPBACK
..................................................................................................................... 18
F
IGURE
13. I
NTERNAL
L
OOP
B
ACK
IN
C
HANNEL
A
AND
B........................................................................................................................ 18
3.0 UART INTERNAL REGISTERS ............................................................................................. 19
T
ABLE
7: UART CHANNEL A AND B UART INTERNAL REGISTERS.............................................................................................. 19
T
ABLE
8: INTERNAL REGISTERS DESCRIPTION. S
HADED
BITS
ARE
ENABLED
WHEN
EFR B
IT
-4=1................................................ 20
4.0 INTERNAL Register descriptions ........................................................................................ 21
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
XR16L2750CJ-0A-EB 功能描述:UART 接口集成電路 Supports L2750 44 ld PLCC, ISA Interface RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel
XR16L2750CJ-F 功能描述:UART 接口集成電路 UART RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel
XR16L2750CM 制造商:EXAR 制造商全稱:EXAR 功能描述:2.25V TO 5.5V DUART WITH 64-BYTE FIFO
XR16L2750CM-0A-EB 功能描述:界面開發(fā)工具 Supports L2750 48 ld TQFP, ISA Interface RoHS:否 制造商:Bourns 產(chǎn)品:Evaluation Boards 類型:RS-485 工具用于評(píng)估:ADM3485E 接口類型:RS-485 工作電源電壓:3.3 V
XR16L2750CM-0B-EB 功能描述:UART 接口集成電路 Supports L2750 48 ld TQFP, PCI Interface RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel
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