REV. 1.1.1 6 1.0 PRODUCT DESCRIPTION The XR16L2450 (L2450) integrates the functions of 2 16C450 Universal Asyn" />
參數(shù)資料
型號(hào)： XR16L2450IM-F
廠商： Exar Corporation
文件頁數(shù)： 27/30頁
文件大小： 0K
描述： IC UART FIFO 1B DUAL 48TQFP
標(biāo)準(zhǔn)包裝： 250
特點(diǎn)： *
通道數(shù)： 2，DUART
FIFO's： 1 字節(jié)
規(guī)程： RS232
電源電壓： 2.25 V ~ 5.5 V
帶故障啟動(dòng)位檢測(cè)功能： 是
帶調(diào)制解調(diào)器控制功能： 是
帶CMOS： 是
安裝類型： 表面貼裝
封裝/外殼： 48-TQFP
供應(yīng)商設(shè)備封裝： 48-TQFP（7x7）
包裝： 托盤
XR16L2450
xr
2.25V TO 5.5V DUART
REV. 1.1.1
6
1.0 PRODUCT DESCRIPTION
The XR16L2450 (L2450) integrates the functions of 2 16C450 Universal Asynchrounous Receiver and
Transmitter (UART). Each UART is independently controlled having its own set of device configuration
registers. The L2450 provides serial asynchronous receive data synchronization, parallel-to-serial and serial-
to-parallel data conversions for both the transmitter and receiver sections. These functions are necessary for
converting the serial data stream into parallel data that is required with digital data systems. Synchronization
for the serial data stream is accomplished by adding start and stops bits to the transmit data to form a data
character (character orientated protocol). Data integrity is ensured by attaching a parity bit to the data
character. The parity bit is checked by the receiver for any transmission bit errors. The electronic circuitry to
provide all these functions is fairly complex especially when manufactured on a single integrated silicon chip.
The L2450 represents such an integration with greatly enhanced features. The L2450 is fabricated with an
advanced CMOS process. The L2450 is capable of operation up to 1.5 Mbps with a 24 MHz clock. With a
crystal or external clock input of 14.7456 MHz the user can select data rates up to 921.6 Kbps.
2.0 FUNCTIONAL DESCRIPTIONS
2.1
CPU Interface
The CPU interface is 8 data bits wide with 3 address lines and control signals to execute data bus read and
write transactions. The L2450 data interface supports the Intel compatible types of CPUs and it is compatible to
the industry standard 16C450 UART. No clock (oscillator nor external clock) is required to operate a data bus
transaction. Each bus cycle is asynchronous using CS#, IOR# and IOW# signals. Both UART channels share
the same data bus for host operations. The data bus interconnections are shown in Figure 3.
.
2.2
5-Volt Tolerant Inputs
The L2450 can accept up to 5V inputs even when operating at 3.3V or 2.5V. But note that if the L2450 is
operating at 2.5V, its VOH may not be high enough to meet the requirements of the VIH of a CPU or a serial
transceiver that is operating at 5V.
2.3
Device Reset
The RESET input resets the internal registers and the serial interface outputs in both channels to their default
state (see Table 8). An active high pulse of at least 40 ns duration will be required to activate the reset function
in the device.
FIGURE 3.
XR16L2450 DATA BUS INTERCONNECTIONS
VCC
OP2A#
DSRA#
CTSA#
RTSA#
DTRA#
RXA
TXA
RIA#
CDA#
OP2B#
DSRB#
CTSB#
RTSB#
DTRB#
RXB
TXB
RIB#
CDB#
GND
A0
A1
A2
UART_CSA#
UART_CSB#
IOR#
IOW#
D0
D1
D2
D3
D4
D5
D6
D7
A0
A1
A2
CSA#
CSB#
D0
D1
D2
D3
D4
D5
D6
D7
IOR#
IOW#
UART
Channel A
UART
Channel B
UART_INTB
UART_INTA
INTB
INTA
UART_RESET
RESET
RS-232 Serial Interface
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