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參數(shù)資料
| 型號(hào)： | XR16C2852IJ |
| 廠商： | EXAR CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 3.3V AND 5V DUART WITH 128-BYTE FIFO |
| 中文描述： | 2 CHANNEL(S), 3.125M bps, SERIAL COMM CONTROLLER, PQCC44 |
| 封裝： | PLASTIC, LCC-44 |
| 文件頁(yè)數(shù)： | 28/42頁(yè) |
| 文件大?。?/td> | 574K |
| 代理商： | XR16C2852IJ |
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á
3.3V AND 5V DUART WITH 128-BYTE FIFO
XR16C2852
REV. 2.0.0
28
EMSR[3:2]: Reserved
EMSR[5:4]: Extended RTS Hysteresis
EMSR[7:6]: Reserved
4.14 FIFO L
EVEL
R
EGISTER
(FLVL) - R
EAD
-O
NLY
The FIFO Level Register replaces the Scratchpad
Register (during a Read) when FCTR[6] = 1. Note
that this is not identical to the FIFO Data Count Reg-
ister which can be accessed when LCR = 0xBF.
FLVL[7:0]: FIFO Level Register
This register provides the FIFO counter level for the
RX FIFO or the TX FIFO or both depending on EM-
SR[1:0]. See Table 12 for details.
4.15 B
AUD
R
ATE
G
ENERATOR
R
EGISTERS
(DLL
AND
DLM) - R
EAD
/W
RITE
The concatenation of the contents of DLM and DLL
gives the 16-bit divisor value which is used to calcu-
late the baud rate:
Baud Rate = (Clock Frequency / 16) / Divisor
See MCR bit-7 and the baud rate table also.
4.16 D
EVICE
I
DENTIFICATION
R
EGISTER
(DVID) - R
EAD
O
NLY
This register contains the device ID (0x12 for
XR16C2852). Prior to reading this register, DLL and
DLM should be set to 0x00.
4.17 D
EVICE
R
EVISION
R
EGISTER
(DREV) - R
EAD
O
NLY
This register contains the device revision information.
For example, 0x01 means revision A. Prior to reading
this register, DLL and DLM should be set to 0x00.
4.18 T
RIGGER
L
EVEL
/ FIFO D
ATA
C
OUNT
R
EGISTER
(TRG) - W
RITE
-O
NLY
User Programmable Transmit/Receive Trigger Level
Register.
TRG[7:0]: Trigger Level Register
These bits are used to program desired trigger levels
when trigger Table-D is selected. FCTR bit-7 selects
between programming the RX Trigger Level (a logic
0) and the TX Trigger Level (a logic 1).
4.19 FIFO D
ATA
C
OUNT
R
EGISTER
(FC) - R
EAD
-O
NLY
This register is accessible when LCR = 0xBF. Note
that this register is not identical to the FIFO Level
Register which is located in the general register set
when FCTR bit-6 = 1.
FC[7:0]: FIFO Data Count Register
Transmit/Receive FIFO Count. Number of characters
in Transmit (FCTR[7] = 1) or Receive FIFO (FCTR[7]
= 0) can be read via this register.
4.20 F
EATURE
C
ONTROL
R
EGISTER
(FCTR) - R
EAD
/
W
RITE
This register controls the XR16C2852 new functions.
FCTR[1:0]: RTS Hysteresis
User selectable RTS# hysteresis levels for hardware
flow control application. After reset, these bits are set
to “0” to select the next trigger level for hardware flow
control. See Table 13 on page 28 for more details.
FCTR[2]: IrDa RX Inversion
Logic 0 = Select RX input as encoded IrDa data.
Logic 1 = Select RX input as active high encoded
IrDa data.
T
ABLE
13: A
UTO
RTS H
YSTERESIS
EMSR
B
IT
-5
EMSR
B
IT
-4
FCTR
B
IT
-1
FCTR
B
IT
-0
RTS#
H
YSTERESIS
(C
HARACTERS
)
0
0
0
0
0
0
0
0
1
±4
0
0
1
0
±6
0
0
1
1
±8
0
1
0
0
±8
0
1
0
1
±16
0
1
1
0
±24
0
1
1
1
±32
1
0
0
0
±40
1
0
0
1
±44
1
0
1
0
±48
1
0
1
1
±52
1
1
0
0
±12
1
1
0
1
±20
1
1
1
0
±28
1
1
1
1
±36
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| XR16C2852IJ-F | 功能描述:UART 接口集成電路 UART RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel |
| XR16C2852IJTR-F | 功能描述:UART 接口集成電路 UART RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel |
| XR-16C450CJ | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:UART |
| XR-16C450CP | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:UART |
| XR-16C452CJ | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:UART |
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